Search found 1 match
- Fri Aug 27, 2021 9:27 pm
- Forum: Sample Code
- Topic: I2S0 Clock (master clock) up to 80MHz derived from APLL clock
- Replies: 14
- Views: 69194
Re: I2S0 Clock (master clock) up to 80MHz derived from APLL clock
Hi jgustavoam! I found your post based on https://github.com/YetAnotherElectronicsChannel/ESP32_DSP_I2S_SETUP I'm still trying to understand the technical documentation, but I have the following situation: I'm using both I2S0 and I2S1. And I seem to understand how the CLK_OUT1 is redirected to GPIO0...