Search found 1216 matches
- Fri Apr 26, 2024 7:50 pm
- Forum: General Discussion
- Topic: ESP32 dualcore example without using FreeRTOS
- Replies: 4
- Views: 231
Re: ESP32 dualcore example without using FreeRTOS
It basically works like this: Code running on core A puts core B into reset (default after power up), writes the memory address from which core B should start executing code into a special register, then un-resets core B. This is, however, not how the cores coordinate during normal operation. For th...
- Thu Apr 25, 2024 10:24 am
- Forum: ESP-IDF
- Topic: InstrFetchProhibited with in IDFv5 upgrade from IDFv4.4
- Replies: 7
- Views: 478
Re: InstrFetchProhibited with in IDFv5 upgrade from IDFv4.4
pbuf_free: deallocating 0x3fcba7cc pbuf_free: custom_free_function 0x3fcba82c This looks interesting... custom_free_function seems to plausibly be a pointer to another data structure here. May be coincidence though. Another thing to check could be: When updating a library you must make sure that al...
- Thu Apr 25, 2024 8:58 am
- Forum: General Discussion
- Topic: Wifi Http simple Server don't read /hello page when I2S Frquency is 96000Hz and I2S_MCLK_MULTIPLE_192
- Replies: 2
- Views: 140
Re: Wifi Http simple Server don't read /hello page when I2S Frquency is 96000Hz and I2S_MCLK_MULTIPLE_192
Code: Select all
ESP_ERROR_CHECK(i2s_channel_init_std_mode(tx_chan, &std_cfg));
- Wed Apr 24, 2024 8:59 pm
- Forum: ESP-IDF
- Topic: Concurrency and trustworthiness of ESP_NOW?
- Replies: 1
- Views: 165
- Wed Apr 24, 2024 7:14 pm
- Forum: General Discussion
- Topic: WireGuard VPN Implementation on ESP32S3
- Replies: 4
- Views: 391
Re: WireGuard VPN Implementation on ESP32S3
I'd expect that a lib like this which runs on C3 and S2 will run on an S3 with little to no modification; especially since, at a glance, I didn't see anything chip-specific in it. (But I think that using the IDF-provided mbedtls version for cryptography would be more efficient than redundantly build...
- Wed Apr 24, 2024 12:36 pm
- Forum: Hardware
- Topic: "Sleep" mode in which IRAM and cache are preserved
- Replies: 12
- Views: 775
Re: "Sleep" mode in which IRAM and cache are preserved
I never can be 100% sure, did I turn off all of what is possible to be turned off Light sleep should turn off almost everything, see https://docs.espressif.com/projects/esp-idf/en/stable/esp32/api-reference/system/sleep_modes.html#id1 Also note the Power Management Locks which may prevent the chip ...
- Tue Apr 23, 2024 7:25 pm
- Forum: ESP-IDF
- Topic: InstrFetchProhibited with in IDFv5 upgrade from IDFv4.4
- Replies: 7
- Views: 478
Re: InstrFetchProhibited with in IDFv5 upgrade from IDFv4.4
The issue is an InstrFetchProhibited... My conclusion was its either a bug with Xtensa GCC compiler upgrade, ESP-IDF upgrade, or MbedTLS upgrade. What do you think? Have I missed something? InstrFetchProhibited may be due to an invalid/corrupt function pointer being called. Reason for that could be...
- Tue Apr 23, 2024 7:09 pm
- Forum: Hardware
- Topic: Is there a way in ESP32 Xtensa assembly to change the content of an address location by "dirting" only one register?
- Replies: 4
- Views: 321
Re: Is there a way in ESP32 Xtensa assembly to change the content of an address location by "dirting" only one register?
No, that's not possible.
One reason is that addresses are 32 bits wide, and our Xtensas' instructions are between 2 and 3 (4) bytes in size. There just isn't enough room in an instruction to encode the instruction and 32 bits of an immediate.
One reason is that addresses are 32 bits wide, and our Xtensas' instructions are between 2 and 3 (4) bytes in size. There just isn't enough room in an instruction to encode the instruction and 32 bits of an immediate.
- Tue Apr 23, 2024 4:15 pm
- Forum: ESP-IDF
- Topic: How properly, under RTOS, to set up the highest priority non-maskable interrupt vector?
- Replies: 23
- Views: 1280
Re: How properly, under RTOS, to set up the highest priority non-maskable interrupt vector?
Yep.
Code: Select all
static void getTicker64_ipc(void* out) {
*(uint64_t*)out = getTicker64();
}
...
uint64_t ticks;
esp_ipc_call_blocking(other_core_id, &getTicker64_ipc, &ticks);
...
- Tue Apr 23, 2024 3:59 pm
- Forum: ESP-IDF
- Topic: How properly, under RTOS, to set up the highest priority non-maskable interrupt vector?
- Replies: 23
- Views: 1280