Search found 84 matches

by Jakobsen
Mon Jun 15, 2020 10:18 pm
Forum: Sample Code
Topic: I2S0 Clock (master clock) up to 80MHz derived from APLL clock
Replies: 7
Views: 6364

Re: I2S0 Clock (master clock) up to 80MHz derived from APLL clock

Hi Gustavo Thanks - I took the time and hacked around with the APLL - the most low level I got was the the call to enable_apll(sdm0, sdm1 ... ) And yes you are right it can be done realtime will out audible effects - I am very happy. This will be next phase of synchronized multi channel audio stream...
by Jakobsen
Mon Jun 15, 2020 8:30 am
Forum: Hardware
Topic: I2S BCK problem
Replies: 8
Views: 734

Re: I2S BCK problem

Full log x40081278: call_start_cpu1 at /home/jkj/esp/esp-idf/components/esp32/cpu_start.c:286 I (0) cpu_start: App cpu up. I (459) heap_init: Initializing. RAM available for dynamic allocation: I (466) heap_init: At 3FFAFF10 len 000000F0 (0 KiB): DRAM I (472) heap_init: At 3FFB6388 len 00001C78 (7 K...
by Jakobsen
Mon Jun 15, 2020 8:24 am
Forum: Hardware
Topic: I2S BCK problem
Replies: 8
Views: 734

Re: I2S BCK problem

Hi No not normal at all - your LR clock should be you sample rate. I do not know of any setup that will end up with 36 Khz. If you able to connect you phone audio source over Bluetooth you will be notified on any sample rate change from the source and the resulting call to set i2s clock with the res...
by Jakobsen
Mon Jun 15, 2020 7:44 am
Forum: Sample Code
Topic: I2S0 Clock (master clock) up to 80MHz derived from APLL clock
Replies: 7
Views: 6364

Re: I2S0 Clock (master clock) up to 80MHz derived from APLL clock

Will take closer look in to you finding tonight - I need a to find a way to fine tune the APLL with out stopping the clock. Until now i just found that the APLL control looks like some IP hooked up on internal I2C - with SW interface through ESP-IDF stack. Happy to find if you work can get me furthe...
by Jakobsen
Wed Jun 03, 2020 9:06 pm
Forum: Hardware
Topic: I2S BCK problem
Replies: 8
Views: 734

Re: I2S BCK problem

Hi Thorbjørn Hard to tell what you are doing wrong - The IDF examples are good high quality so I guess you have something not right in you hardware setup. Try to upload a picture or 2 - Make sure your ground are good grounds and your supply rails are stable. 5V from USB, 3V3 from esp32 module to you...
by Jakobsen
Wed May 27, 2020 1:26 pm
Forum: General Discussion
Topic: wifi + I2s
Replies: 5
Views: 458

Re: wifi + I2s

There are lots of good example out there that takes a http based audio stream from the internet via WIFI and output audio via I2S to a codec/audio amplifier. In case you want to use your mobile to source the audio you can use the bt audio sink examble. If you require Wifi one option is to wait for s...
by Jakobsen
Mon May 11, 2020 9:15 pm
Forum: ESP32 ADF
Topic: A2dp sink volume control?
Replies: 5
Views: 830

Re: A2dp sink volume control?

Hi MooaLot Correct design practice would be control volume in as close the speaker as possible - so if your last point of control is an external DAC find out if it has a volume control to offer over I2C. If that is not the case you are back to apply you volume to you PCM sample before you pass them ...
by Jakobsen
Fri May 01, 2020 7:41 am
Forum: Showcase
Topic: Full audio sub-system based on WROVER
Replies: 3
Views: 1185

Re: Full audio sub-system based on WROVER

Wau - well designed and impressive feature list

I was notified on your project yesterday.
Look forward to give it at try on my hardware as well.
Jakobsen
by Jakobsen
Sat Apr 04, 2020 8:04 pm
Forum: Hardware
Topic: I2S DMA
Replies: 4
Views: 2637

Re: I2S DMA

Missing a lot ...

It is only a couple of lines from a signal generator component.

You can check out the full project from the repo :
https://github.com/jorgenkraghjakobsen/sig_gen.git

/j

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