Search found 89 matches

by Jakobsen
Tue Jan 04, 2022 11:39 pm
Forum: ESP-ADF
Topic: filter_resample stereo to mono incl. mix right channel to left channel
Replies: 2
Views: 9725

Re: filter_resample stereo to mono incl. mix right channel to left channel

Easy todo if you step out of the IDF
If you do take a look at my dsp_processor componet in github.com/jorgenkraghjakobsen/snapclient.git
/Jørgen
by Jakobsen
Sun Feb 07, 2021 10:54 pm
Forum: ESP-IDF
Topic: Trying to reduce TCP Socket Latency
Replies: 3
Views: 6377

Re: Trying to reduce TCP Socket Latency

Also make sure you have disabled package aggregation in you tcp/ip stack

in
Menuconfig > component config --> WIFI ---> WiFi AMPDU TX <--- Disable
Menuconfig > component config --> WIFI ---> WiFi AMPDU RX <--- Disable

/J
by Jakobsen
Sun Feb 07, 2021 10:36 pm
Forum: ESP-IDF
Topic: How to use simultaneously A2D, AVRC and SPP in a ESP32?
Replies: 2
Views: 4849

Re: How to use simultaneously A2D, AVRC and SPP in a ESP32?

Yes
Check out my https://github.com/jorgenkraghjakobsen/merus_bt.git
I connect from android SPP client to control volume, dsp flow etc and monitor amplifier state
Integrates very well.
/j
by Jakobsen
Thu Sep 03, 2020 9:40 pm
Forum: ESP-ADF
Topic: How to play a beep during MP3 playback?
Replies: 4
Views: 11574

Re: How to play a beep during MP3 playback?

Hi Felix

Check the dsp_processor in my githup repo

https://github.com/jorgenkraghjakobsen/merus_bt

It should be straigh forward to mix in a beep - but please do a nice beep - not just 440hz sine.

No im not working in the ADF.

Hope that will give you some thing to work with.
/Jakobsen
by Jakobsen
Mon Jun 15, 2020 10:18 pm
Forum: Sample Code
Topic: I2S0 Clock (master clock) up to 80MHz derived from APLL clock
Replies: 14
Views: 68520

Re: I2S0 Clock (master clock) up to 80MHz derived from APLL clock

Hi Gustavo Thanks - I took the time and hacked around with the APLL - the most low level I got was the the call to enable_apll(sdm0, sdm1 ... ) And yes you are right it can be done realtime will out audible effects - I am very happy. This will be next phase of synchronized multi channel audio stream...
by Jakobsen
Mon Jun 15, 2020 8:30 am
Forum: Hardware
Topic: I2S BCK problem
Replies: 8
Views: 11332

Re: I2S BCK problem

Full log x40081278: call_start_cpu1 at /home/jkj/esp/esp-idf/components/esp32/cpu_start.c:286 I (0) cpu_start: App cpu up. I (459) heap_init: Initializing. RAM available for dynamic allocation: I (466) heap_init: At 3FFAFF10 len 000000F0 (0 KiB): DRAM I (472) heap_init: At 3FFB6388 len 00001C78 (7 K...
by Jakobsen
Mon Jun 15, 2020 8:24 am
Forum: Hardware
Topic: I2S BCK problem
Replies: 8
Views: 11332

Re: I2S BCK problem

Hi No not normal at all - your LR clock should be you sample rate. I do not know of any setup that will end up with 36 Khz. If you able to connect you phone audio source over Bluetooth you will be notified on any sample rate change from the source and the resulting call to set i2s clock with the res...
by Jakobsen
Mon Jun 15, 2020 7:44 am
Forum: Sample Code
Topic: I2S0 Clock (master clock) up to 80MHz derived from APLL clock
Replies: 14
Views: 68520

Re: I2S0 Clock (master clock) up to 80MHz derived from APLL clock

Will take closer look in to you finding tonight - I need a to find a way to fine tune the APLL with out stopping the clock. Until now i just found that the APLL control looks like some IP hooked up on internal I2C - with SW interface through ESP-IDF stack. Happy to find if you work can get me furthe...
by Jakobsen
Wed Jun 03, 2020 9:06 pm
Forum: Hardware
Topic: I2S BCK problem
Replies: 8
Views: 11332

Re: I2S BCK problem

Hi Thorbjørn Hard to tell what you are doing wrong - The IDF examples are good high quality so I guess you have something not right in you hardware setup. Try to upload a picture or 2 - Make sure your ground are good grounds and your supply rails are stable. 5V from USB, 3V3 from esp32 module to you...