And this is my simplified i2s_parallel.c for 8bit lcd mode ... #include <stdio.h> #include <stdint.h> #include <stddef.h> #include <string.h> #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/semphr.h" #include "freertos/queue.h" #include "soc/i2s_struct.h" #include "soc/i...

It's not the pixels that are swapped, it's the actual bytes getting loaded into the I2S path. So instead of just swapping the pixels around, you should swap around the way you write into the I2S buffer. If you don't, the sync signals will still be written 'straight' and me emitted in the wrong plac...

ESP_Sprite, you were right about the weird ordering, I noticed this only with a bitmap image. Had to swap odd and even bytes in the source image buffer before extracting the 4bit data for each packet. But i still have a problem with the line synchronization, left and right borders are swapped. Still...

Also, the clock frequency needs to be configured as twice the required clock frequency.

I have a stable image on the LCD, and the pixel left-to-right ordering corresponds to the byte ordering in the frame buffer. ESP_Sprite, thanks for the help ! Just have a problem with the line synchronization. col 0 of the image is offset to the right in the LCD. In my grab of the original working l...

Hey, just wanted to confirm if this piece of code from i2s_parallel.c (led_panel project) void i2s_parallel_flip_to_buffer(i2s_dev_t *dev, int bufid) { int no = i2snum(dev); if (i2s_state[no] == NULL) return; lldesc_t *active_dma_chain; if (bufid == 0) { active_dma_chain = (lldesc_t*)&i2s_state[no]-...

I made my own TAS5753MD based board. According to the datasheet, PVDD minimum is 4.5V, but I've only tested it at > 7V ( 2S and 3S lipoly battery packs). Unfortunately, I wasn't able to use TI's Purepath console software to do all the nice software enhancements like equalization, gain limiting etc. ...

Thanks, I will have a go at it !

Had a look at the TRM again, it mentions on pg 242 that the LCD mode databus is 24bits. I don't see any specific mention of 8bit or 16bit bus width. Also, the two frame transmit modes "forms" don't seem to map to my scenario. Assuming D0, D1 ... are data packets, I would need one clock for each 8bit...

ESP_Sprite, that's good news. I will go through the TRM. I did have a look a couple days ago, but at first glance did not see anything specific to 8bit bus width. I would appreciate it if you could dig up and post your 8bit parallel test code. I will have additional questions anyway, and it would sa...