Yes
Nice job @Espressif - BT audio packages comming through

Hi Buddy Hop you got some fresh air - I am jorgenkraghjakobsen at github - Stil working on by git foo - think I have seen the light at the end of the tunnel but still a couple of nights before I will get there. Just let me start to do a pull request - I only change 2 files and added 2. Still not sur...

Hi Buddy I have added 32 bit audio support and setup procedure for Merus audio amplifier. I have adds some files and commited the change to my local repo - Now I want to push the stuff to your master branch - what to do ? git push gives me access denied - other options. In my old develop branch i ha...

Hi Buddy
Just did some simple ccount sampling pre and post code block. I have a float and a fixed point version of my DSP/Biquad. Initial did the profiling to learn dif between float and fixed math.
Look forward to see your re-factored code.
/j

Hi Buddy

Nice - I will give it at try over the weekend - Regarding Git - I just have to learn.

Have you notices performance increase after the idf 2.0 rc update. My DSP/Biquad runs 30-40% faster...

Thanks for the head up on the hack chat
/jørgen

Hi Just a small update from here - I did some DSP/biquads on the audio stream and got some experience on how far it can be pushed. 1. Float math very easy to work with and only low overhead compared to fixed point math 2. IDF rev 2.0 rc update gave 50 % better performance on my float DSP/biquad impl...

Hi I also found that my hot fix works for both 100kbps and 400kbps. I measure frequency on the 8 first scl clock only. period of 9 th clock (ACK) is still long and random. From a system perspective i would never relay on any derived frequency from a i2c interface - Do you have any reason for doing s...

Hi My hot fix for the i2c_scl clock below I tried also to change I2C[i2c_num]->sda_sample.time = half_cycle - but did not get to a stable setup. From time to time the driver gets to unrecoverable stated with random data on data/clk line :-( I2C[i2c_num]->fifo_conf.nonfifo_en = 0; } //set frequency 7...

Did some i2c scl measurements at 100, 200, 300, 400 and 800 kbps Looks like (last plots in this post) we have a 190 ns constant unaccounted delay per cycle scl for a 160MHz and 240MHz system clock using the idf i2c driver - so must be related to amba bus frequency. Any way sub the 190ns in the i2c_s...

Hi
I did 800 kbps just to check if how the system scaled. I was ok but with const clock stretch period.
Yes I will measure some exact frequency and report back. /j