Quite possibly. spi_master.c has had quite a few changes & more than a sprinkling of 'atomic'. The CAN SPI interrupt was allocated on core 0. The CAN SPI transactions were always initiated on core 1. So TX (core 1) was: (a) Queue (b) Enable ISR RX ISR (core 0) was: (1) Check each CS Queue (2) If no ...

I have been doing most of my tests on v3.2-dev-760-ga0d2dd03 as I need ESP32 CAN and the soc changes etc.

The soak has run for 24 hours now and would normally fail within 5 minutes.
If you have thoughts on what the issue might have been then I would love to hear.

Thanks.
I think that the issue has been fixed in v3.2-beta1.
There are a lot of merged changes though so I am not sure. Need to soak test.
Would love to know the mechanism.

Added some interrupt diagnostics. When VSPI (the CAN) transaction times out: Owning CPU (handle->host->intr): 0 Executing CPU (xPortGetCoreID): 1 uxQueueMessagesWaiting(handle->trans_queue): 1 Interrupt Source: 0x1f, Number: 0x12 DPORT_PRO_INTR_STATUS_0_REG: 0xd0000000 DPORT_APP_INTR_STATUS_0_REG: 0...

Thanks. I have a single GPIO interruptin the main application as well (MCP2515 CAN). I have not yet included the GPIO INT in the MWE. My application does seem sensitive to Ethernet though. I scan read the IDF code. The SPI hosts seem quite seperate. Each driver receieves its own interupt and runs fr...

Thanks, yes your report seems very similar but my application still fails when SPI activity was pinned to core 0 (achieved 30 min which is longest run so far). I will go back & ensure that the SPI bus & devices are created from core 0. I also use Ethernet RMII. There are some broadcasts on my test n...

I removed the ESP32 CAN driver and the PSRAM profiler. The application stills locks up waiting for a CAN SPI response (VSPI). I believe that VSPI and HSPI access queues from their respective interrupt handlers. That said then I don't see how the conflict may arise. Stacks are 4096 so I doubt that's ...

Agreed. SPI latency should not matter except that it opens a larger concurrent event window. Yes, 'host' means SPI host. 'core' means CPU. Note also that the CAN SPI device was created before the SPI FLASH device (not that that should matter as different hosts). Moved CAN SPI SCHEDULER to core 0 (al...

Thanks for the interest. I have started adding xPortGetCoreID() to debug statements so that I am sure. There are sleeps in each harness however. I should add that the CAN test runs the SPI controller back to back with the ESP32 CAN. The program is also >> bigger than IRAM and I have not set IRAM pro...

I have started integrating my device drivers. I have two SPI device. A CAN controller on VSPI and a FLASH on HSPI. The CAN transactions use spi_device_transmit() (DMA channel = 0). CAN SPI access is driven on core 1 (to ensure low latency). The SPI test harness runs on core 0 and sends commands to c...