This is what NVS is for http://esp-idf.readthedocs.io/en/latest ... flash.html

Interested to know power consumption vs pulse rate and max possible pulse rate. Also can you post ulp template next? Current is 5uA in sleep phase and 13mA in active phase (which is possible to reduce by lowering the APB/CPU frequencies from 40 down to 2MHz at the entry of the wake stub... but i ne...

Another option might be using the pulse as the rtc clock input at the peril of getting stuck sleeping if the pulses stop. I have created an example which illustrates deep sleep'ing and counting low pulses on GPIO0 Interested to know power consumption vs pulse rate and max possible pulse rate. Also c...

Yes but we care about edges and how digital bck compares to jitter from bpll src https://esp32.com/viewtopic.php?f=17&t= ... t=20#p4727

Hmm I see.. and resulting jitter on i2s_bck ?

Anyone try with 12mhz apll clock? How is jitter?

qjones wrote:I see the dummy bits, and I believe I see where to set the clock disable in spi_dev_t struct definition. But I don't see an easy way to set this without a modified spi_master.c.

Yes, looks like the driver doesn't support the usr_dummy_idle option yet.

Sounds like a job for dummy bits and disable clk during dummy phase.