Atomics are supported, and as long as you use a 32-bit atomic, access is a lot faster as the hardware will take care of atomicity rather than needing code for critical sections.

You're replying to a 4-year old thread; I was talking about the 'original' ESP32 (no -S or -C suffix). I think it's indeed supported again on later chips. I guess we didn't bother to implement it in the ULP toolchain yet, though.

Where and how is 'var' defined? You sure it doesn't go out of scope?

You probably want to look at core dumps . Basically, you create a partition for a core dump, and whenever the ESP32 crashes, it writes relevant data there and reboots. After that, you can detect a coredump was created and do whatever with it; for instance, for systems I maintain, it uploads them via...

They have flash, but it's not necessarily manufactured by XMC.

Can you explain this line?

I cannot comment on any current activities / plans wrt cooperating with companies (mostly because I have no clue but also because I'm not sure if that's public), but we've always been forthcoming in documenting our stuff (both in the form as technical reference manuals as well as source code, e.g. t...

My colleagues are interested in RISC-V. Unfortunately, the product selector doesn't appear to let you filter for the CPU type (Xtensa or RISC-V). For most people, that is pretty uninteresting as it's abstracted away by any SDK you'd use it with. FWIW, at this point the C2, C3, C6, H2 and the future...

Did you copy 60-openocd.rules to your udev rules directory?

I tried to build the same project with eclipse, according to your instructions, but faced the similar linker problems. Are you using another toolchain than gcc? If you post that error here, you may have a better chance of us being able to solve it. Could you please tell me the documents names ( the...