UART & pins typically used by USB bridge?

bitbang3r
Posts: 3
Joined: Sat May 26, 2018 12:17 am

UART & pins typically used by USB bridge?

Postby bitbang3r » Fri Nov 15, 2019 8:51 am

I have a HiLetGo Wemos Lolin32 clone with SSD1306 OLED whose pinout is exactly like this one:

Image

From the silkscreened legend on the board, it's obvious that they're associating UART0 with the pins mapped to GPIO1 and GPIO3.

As I understand it, any of the 4 UART functions (TX, RX, CTS, RTS) for any of the 3 UARTs can be mapped to (almost) any pin (though I believe the pins identified as SVP/GPIO36, SVN/GPIO39, GPIO0, GPIO2, and GPIO12 are off-limits for UART use).

That said... which UART is typically bound to the UART-USB bridge?

If it's bound to UART0, does that mean that the pins on the breakout board identified as RX0 and TX0 are probably hardwired to the USB-UART bridge chip & can't be used for any other purpose? Or would a board like this typically use UART1 or UART2, and bind the UART used by the USB-UART bridge to ESP32 pins that WEREN'T directly exposed by the header, precisely to ensure that the ones exposed BY the header could be freely used without risk of interfering with the chip's future flashability, debuggability, etc?

WiFive
Posts: 3529
Joined: Tue Dec 01, 2015 7:35 am

Re: UART & pins typically used by USB bridge?

Postby WiFive » Fri Nov 15, 2019 8:37 pm

If it's bound to UART0, does that mean that the pins on the breakout board identified as RX0 and TX0 are probably hardwired to the USB-UART bridge chip
Yes

bobtidey
Posts: 43
Joined: Mon Jun 18, 2018 2:24 pm

Re: UART & pins typically used by USB bridge?

Postby bobtidey » Fri Nov 15, 2019 10:09 pm

I don't know about this board but many dev boards put a series resistor between the TX of the bridge and the cpu RX. This allows an external signal to override it without causing a conflict. The TX from the cpu to the RX of the bridge is not a problem. The resistor used can be quite low (e.g. 470 Ohm) so if driving from an external signal this must have decent drive capabilities to handle that

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