IO0 Internal Pullup Disabled?

nebkat
Posts: 1
Joined: Sat Feb 23, 2019 1:04 pm

IO0 Internal Pullup Disabled?

Postby nebkat » Sat Feb 23, 2019 1:10 pm

I have designed my own board for ESP32-WROOM-32D but I'm having issues with boot mode selection. It seems that the internal pullup of IO0 is not working, as it boots to download mode by default. Checking the voltage at boot it is indeed at 0V rather than high. After connecting a 10k resistor to 3V3 it boots fine. Before this, IO0 was left unconnected.

As far as I know IO0 is not required to have an external pullup, and it doesn't have one on the DevKitC. Could it be possible that the internal pullup had been disabled or damaged?

DurandA
Posts: 17
Joined: Thu Nov 26, 2015 11:51 pm

Re: IO0 Internal Pullup Disabled?

Postby DurandA » Tue Feb 26, 2019 10:30 pm

I got the exact same problem. I just soldered a new revision of a board I am developing and it goes to download mode without a pullup resistor. I did not have this problem with older chips.

ESP_Angus
Posts: 2182
Joined: Sun May 08, 2016 4:11 am

Re: IO0 Internal Pullup Disabled?

Postby ESP_Angus » Wed Feb 27, 2019 12:01 am

I don't know, but it's possible the internal pullup is not strong enough on all chips. I'll ask the hardware team to check on this and get back to you.

ESP_Stone
Posts: 19
Joined: Mon Nov 19, 2018 3:59 am

Re: IO0 Internal Pullup Disabled?

Postby ESP_Stone » Wed Feb 27, 2019 9:52 am

Will you guys please post your schematic here? Thanks.

DurandA
Posts: 17
Joined: Thu Nov 26, 2015 11:51 pm

Re: IO0 Internal Pullup Disabled?

Postby DurandA » Wed Feb 27, 2019 7:56 pm

Here you are:
Schematic_Reflow_20190227204311.pdf
(90.94 KiB) Downloaded 144 times
Please note that IO0 is wired to a ISP header, but IO0 is left unconnected in the header.

ESP_Stone
Posts: 19
Joined: Mon Nov 19, 2018 3:59 am

Re: IO0 Internal Pullup Disabled?

Postby ESP_Stone » Thu Feb 28, 2019 2:02 am

I suggest you add one 1uF cap close to ENABLE. Like below showed:

ESP_Stone
Posts: 19
Joined: Mon Nov 19, 2018 3:59 am

Re: IO0 Internal Pullup Disabled?

Postby ESP_Stone » Thu Feb 28, 2019 2:05 am

Sorry, add the picture.
Attachments
RC circuit  on enable.png
RC circuit on enable.png (98.14 KiB) Viewed 3143 times

DurandA
Posts: 17
Joined: Thu Nov 26, 2015 11:51 pm

Re: IO0 Internal Pullup Disabled?

Postby DurandA » Thu Feb 28, 2019 2:22 am

C5 of 1uF is placed very close to ENABLE. However, I do not have that R2 resistor. I guess its purpose is to isolate the analog ground from the digital ground.
Screenshot_2019-02-28 EasyEDA - A Simple and Powerful Electronic Circuit Design Tool.png
Screenshot_2019-02-28 EasyEDA - A Simple and Powerful Electronic Circuit Design Tool.png (103.9 KiB) Viewed 3129 times

ESP_Sprite
Posts: 3911
Joined: Thu Nov 26, 2015 4:08 am

Re: IO0 Internal Pullup Disabled?

Postby ESP_Sprite » Thu Feb 28, 2019 10:13 am

You actually do have the equivalent of R2 in the schematic; it's R6 on your PCB. What you do not have is an 1uF cap from EN to GND. C5 on your PCB is a decoupling cap, the same as C2 in Stone's schematic.

DurandA
Posts: 17
Joined: Thu Nov 26, 2015 11:51 pm

Re: IO0 Internal Pullup Disabled?

Postby DurandA » Thu Feb 28, 2019 1:08 pm

Thanks @ESP_Stone and @ESP_Sprite, it seems I was very tired when reading this. Indeed, this capacitor is part of Figure 4: ESP32-WROOM-32 Peripheral Schematics from ESP32-WROOM-32 datasheet and I somehow missed it.

I will solder an extra capacitor and report back. Let's see if @nebkat issue is related to mine.

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