From this page in the docs: https://docs.espressif.com/projects/esp ... t_device_t
The default CS lines for the HSPI and VSPI buses are GPIO 15 and 5 respectively. That would be one of the three CS lines (for each bus) as described.SPI1, HSPI and VSPI all have three chip select lines, allowing them to drive up to three SPI devices each as a master.
Also from the docs:
So for maximum speed of the bus, the defaults for MISO, MISO, SCLK and CS are significant as they route through the IO_MUX rather than the GPIO_MUX.If the driver is configured with all SPI signals set to their specific IOMUX pins (or left unconnected), it will bypass the GPIO matrix. If any SPI signal is configured to a pin other than its IOMUx pin, the driver will automatically route all the signals via the GPIO Matrix.
However, the docs don't seem to indicate which GPIO pins should be used for the other two (non-default) CS pins on each bus to ensure they also are routed through the IO_MUX and thereby maximizing the bus speed..
Anyone have any insight?