Timer divider and frequency

tosemusername
Posts: 6
Joined: Tue Feb 05, 2019 5:28 pm

Timer divider and frequency

Postby tosemusername » Mon Sep 09, 2019 5:50 pm

https://docs.espressif.com/projects/esp ... troduction
The ESP32 chip contains two hardware timer groups. Each group has two general-purpose hardware timers. They are all 64-bit generic timers based on 16-bit prescalers and 64-bit up / down counters which are capable of being auto-reloaded.
and then...
Divider: Sets how quickly the timer’s counter is “ticking”. The setting divider is used as a divisor of the incoming 80 MHz APB_CLK clock.
So divider effectively sets the value of the prescaler? As in the prescaler is not fixed?

Also
https://github.com/espressif/esp-idf/bl ... soc.h#L242
If that's that's the timer frequency, shouldn't 80 MHz above be 5MHz?

What am I missing here?

ESP_Dazz
Posts: 136
Joined: Fri Jun 02, 2017 6:50 am

Re: Timer divider and frequency

Postby ESP_Dazz » Thu Sep 12, 2019 1:45 pm

An 80MHz APB Clock is fed into the entire Timer Group. Each timer then takes 80MHz APB clock and divides it down via the prescaler to a frequency of their own liking. How much the 80MHz clock is divided down by is determined by the value set in the prescaler (i.e. the Divider). The divider can take be any 16-bit value.

For example, if a timer needs to tick (count up/down) at 800KHz, it would set its divider to 100. Because each timer has it's own prescaler, multiple timers can operate at different frequencies simulatneously.
tosemusername wrote: Also
https://github.com/espressif/esp-idf/bl ... soc.h#L242
If that's that's the timer frequency, shouldn't 80 MHz above be 5MHz?
This seems like some legacy code. Can see that macro being used anywhere else in IDF. But the macro is still correct as it indicates that for a timer to operate at 5MHz, the prescaler for the timer will be 16 (i.e. >> 4).

tosemusername
Posts: 6
Joined: Tue Feb 05, 2019 5:28 pm

Re: Timer divider and frequency

Postby tosemusername » Tue Sep 17, 2019 5:24 pm

Oh well, I just posted another closely related question on the forums and I can't find it due to it being submitted to approval, because I thought this one had not been posted and I didn't see any notification until after I did it.

I would like the discussion to continue on the other thread, as I go a little bit more specific about my doubts, but on the off chance it's not feasible, my follow up is this:
ESP_Dazz wrote:
Thu Sep 12, 2019 1:45 pm
An 80MHz APB Clock is fed into the entire Timer Group. Each timer then takes 80MHz APB clock and divides it down via the prescaler to a frequency of their own liking. How much the 80MHz clock is divided down by is determined by the value set in the prescaler (i.e. the Divider).

For example, if a timer needs to tick (count up/down) at 800KHz, it would set its divider to 100. Because each timer has it's own prescaler, multiple timers can operate at different frequencies simulatneously.

This seems like some legacy code. Can see that macro being used anywhere else in IDF. But the macro is still correct as it indicates that for a timer to operate at 5MHz, the prescaler for the timer will be 16 (i.e. >> 4).
I guess that clarifies pretty much everything.
Does it mean I can have the timer ticking at 40MHz?
The divider can take be any 16-bit value.
Except 0 (obviously), but also 1. Why can it not be 1? Because of the division operation or some other cost involved in prescaling the clock?

ESP_Dazz
Posts: 136
Joined: Fri Jun 02, 2017 6:50 am

Re: Timer divider and frequency

Postby ESP_Dazz » Thu Sep 19, 2019 4:01 pm

tosemusername wrote: Does it mean I can have the timer ticking at 40MHz?
Yep, just set the divider to 2
tosemusername wrote: Except 0 (obviously), but also 1. Why can it not be 1? Because of the division operation or some other cost involved in prescaling the clock?
It's a hardware limitation. A Timer's internal logic operates according to APB clock. My guess is if the internal logic is operating at the same or lower frequency compared to the counter, there would be timing issues. Here's a excerpt about the divider registers form the ESP32 TRM.
Each timer uses the APB clock (APB_CLK, normally 80 MHz) as the basic clock. This clock is then divided down by a 16-bit precaler which generates the time-base counter clock (TB_clk).

The prescaler can divide the APB clock by a factor from 2 to 65536. Specifically, when TIMGn_Tx_DIVIDER is either 1 or 2, the clock divisor is 2; when TIMGn_Tx_DIVIDER is 0, the clock divisor is 65536. Any other value will cause the clock to be divided by exactly that value

tosemusername
Posts: 6
Joined: Tue Feb 05, 2019 5:28 pm

Re: Timer divider and frequency

Postby tosemusername » Tue Sep 24, 2019 10:00 pm

Awesome. A couple more questions...

https://docs.espressif.com/projects/esp ... interrupts
When handling an interrupt within an interrupt serivce routine (ISR)
I don't really get the wording here. Interrupts are handled inside ISRs, right? Since that's obvious, it must not be what it means.
1) Can someone clarify it?

The documentation says the alarm is disabled after triggered. But it says nothing about the counter, which might indicate that all operations on it are performed explicitly. As such, if I enable the counter's autoreload, the alarm triggers and it's disabled. I was under the impression that when the alarm triggers and the counter autoreloads, the alarm is disabled, and the counter stopped, so I don't have to manually set it to 0 again. This is because I want to use it as an occasional timer instead of a periodic one.
2) So is that the case? Or do I have to call `timer_set_counter_value` to set the counter to 0 in every occasion?

3) What's the difference between Timer and High Resolution Timer? Is the latter only a wrapper around the former? Which one carries less overhead, if any?

tosemusername
Posts: 6
Joined: Tue Feb 05, 2019 5:28 pm

Re: Timer divider and frequency

Postby tosemusername » Mon Sep 30, 2019 7:31 pm

Bumping...

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