[Answered] SPI Read Register Delay

qjones
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Joined: Sun Feb 19, 2017 12:17 am

[Answered] SPI Read Register Delay

Postby qjones » Wed Mar 01, 2017 5:35 pm

Hi,

Quick question here. I have been using the esp-idf spi api successfully by using the spi_device_transmit api. However I have run into a situation with a device that I need to insert a 75 us delay between writing the register address to read from and the time the data is ready to read. The way I understand the spi_device_transmit is that everything is queued up into a transaction I do not see any way to insert any delays.

Pseudo of what I need to do:

SetChipSelectPin(0);
SPIWrite(RegisterAddress);
Delay(75us); // How do I add this??
rxData = SPIWrite(RegisterAddress);
SetChipSelectPin(1);

Hopefully I explained my question. I am a little new to using the SPI bus. So my apologies if I am missing something easy.

Thanks!
Last edited by qjones on Thu Mar 02, 2017 4:04 pm, edited 1 time in total.

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kolban
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Re: SPI Read Register Delay

Postby kolban » Wed Mar 01, 2017 7:34 pm

Just a guess ... but instead of one SPI transaction with two data interactions ... could we not use two SPI transactions with one data interaction each?

For example:

Code: Select all

spi_device_transmit();
delay(period);
spi_device_transmit();
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qjones
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Re: SPI Read Register Delay

Postby qjones » Wed Mar 01, 2017 10:35 pm

I thought about this. I just have not had a chance to try it yet. I am still new to the ends and outs of the SPI bus particularly now that I am trying to write some of my own device interfaces. However the way I understand it is that the CS line will get toggled with each of the spi_device_transmit(). I could assume that the data loaded from the read register on the 1st transaction would just get shifted out on the next go around. But I feel like there will be a chance to miss some data depending on the clock and timings that are also happening on the back end for setup. Just trying to make sure I am not doing any bad practices or am not trying to code around some easy. Worst case I will just use the esp32-hal-spi api from the arduino side. Seems unnecessary but not the end of the world while everything gets ironed out on this new chip.

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kolban
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Re: SPI Read Register Delay

Postby kolban » Wed Mar 01, 2017 11:01 pm

For my own curiosity, what is the nature of the SPI slave device? Do we have a reference to a data sheet on it?
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qjones
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Joined: Sun Feb 19, 2017 12:17 am

Re: SPI Read Register Delay

Postby qjones » Wed Mar 01, 2017 11:46 pm

It is the ADNS-3080 optical mouse sensor. Very cool board. I am needing to use it for some basic image processing and possibly for optical flow position calculations on a project. It's an older chip and this seems to be the best link.

https://people.ece.cornell.edu/land/cou ... s_3080.pdf

On page 11 you will see the register read delays of 50us and 75us for the motion registers. There have been plenty of arduino and mbed libraries that have interfaced it but all those seem to have the capabilities to set these intermittent delays in the SPI transmission. I haven't hooked the esp32 up to a scope or analyzer yet so for all I know this 75us delay is already covered.... Anyway it would make a great chip for one of your video snippets :)

Thanks,

ESP_Sprite
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Re: SPI Read Register Delay

Postby ESP_Sprite » Thu Mar 02, 2017 1:34 am

Hmm, the ESP32 may also have the hardware to do something like this... lemme check; I have a driver update in the queue anyway, may as well enable this when the hardware can do it.

Edit: Ah, this is not going to keep the CS from going high while waiting, by the way. The SPI bus in the ESP32 is pretty optimized for high-speed transfers, and in general changing timing parameters (which is what you want to do with your delay) is not common. If you truly want to do this, you may need to implement SPI in software by bitbanging. That being said, I am pretty sure the chip you have in mind won't mind the read and write being in separate transfers.

WiFive
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Re: SPI Read Register Delay

Postby WiFive » Thu Mar 02, 2017 1:54 am

Sounds like a job for dummy bits and disable clk during dummy phase.

ESP_Sprite
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Re: SPI Read Register Delay

Postby ESP_Sprite » Thu Mar 02, 2017 2:13 am

Ah, you're right, you may be able to get around it that way.

qjones
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Re: SPI Read Register Delay

Postby qjones » Thu Mar 02, 2017 2:51 am

WiFive wrote:Sounds like a job for dummy bits and disable clk during dummy phase.
Can you explain a little further. I see the dummy bits, and I believe I see where to set the clock disable in spi_dev_t struct definition. But I don't see an easy way to set this without a modified spi_master.c. I will keep looking but I am probably missing something here... I thought I had the spi portion vetted out and go figure I need to use the one random chip doing something atypical. Keeps it exciting anyway.

Thanks!

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loboris
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Re: SPI Read Register Delay

Postby loboris » Thu Mar 02, 2017 7:37 am

qjones wrote:... However the way I understand it is that the CS line will get toggled with each of the spi_device_transmit()...
You can use transactions without CS and (de)activate CS pin in software:

Code: Select all

    spi_device_interface_config_t devcfg={
        .clock_speed_hz=10000000,               //Clock out at 10 MHz
        .mode=0,                                //SPI mode 0
        .spics_io_num=-1,                       //NO CS PIN USED
    };
Then you can activate CS (set low any pin used as CS) before first transaction, execute transaction, wait some time, execute the 2nd transaction and deactivate CS.

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