ESP32 PSRAM support

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rudi ;-)
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Re: ESP32 PSRAM support

Postby rudi ;-) » Sat Jun 03, 2017 6:56 am

ESP_Sprite wrote:

..
You can download the beta esp-idf and the toolchain from the usual spots (https://github.com/espressif/esp-idf and https://github.com/espressif/crosstool-NG) but be sure to switch to the psram-compatible branches. For esp-idf, the branch is called 'feature/psram_malloc', for the toolchain it is called 'xtensa-1.22.x-ext_ram_patch'. Note that there are no binaries available for the toolchain, you will need to build it from source. For the different OSses, this is documented here: Linux Mac (Sorry, no Windows support for this yet.). Note: In order to get the psram version, in the instructions at the 'git clone' command, replace 'xtensa-1.22.x' with 'xtensa-1.22.x-ext_ram_patch'. For esp-idf, just clone esp-idf as usual, then do 'git checkout feature/psram_malloc'.


after you have do 'git checkout feature/psram_malloc'
be sure you do this step then :
git submodul update --init

-> toolchain successful

esp8266@esp8266-VirtualBox:~/esp32psram/xtensa-esp32-elf/bin$ xtensa-esp32-elf-gcc --version
xtensa-esp32-elf-gcc (crosstool-NG crosstool-ng-1.22.0-64-g47d56eb) 5.2.0
Copyright (C) 2015 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.


-> esp-idf successful
-> hello_world successful

wrover modul still revision 0
pSRAM_REV0.jpg
pSRAM_REV0.jpg (192.05 KiB) Viewed 736 times


can we check on Rev0 wrover the pSRAM?

edit:

tested -
--- ok - no pointer --

Code: Select all

/*spiram*/
#include "esp_heap_alloc_caps.h"
// #include "../spiram.h" /*** void enable_spi_sram(); ***/

...
uint32_t* buffer = pvPortMallocCaps(4*1024*1024, MALLOC_CAP_SPISRAM);
    if (buffer==NULL) {
       printf("could not create SPIRAM Pointer\n");
    } else {
      printf("RAM init done\n");
    }
   


Code: Select all

void enable_spi_sram();



best wishes
rudi ;-)
Last edited by rudi ;-) on Sat Jun 03, 2017 8:19 am, edited 1 time in total.
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Re: ESP32 PSRAM support

Postby rudi ;-) » Sat Jun 03, 2017 8:18 am

ok - Rev0 does not support pSRAM

With these Wrover'n I had actually already assumed.
PSRAM would be supported.
Because they were also installed on it.
Could not you test this before?

i.e. You can remove them now because they are not usable.
Very unfortunate - and honest - I am a little sad about it.
But ok - now certainty is there and now we know it - away with the theme.
the summer comes.

thank you for your effort Jeroen!
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Re: ESP32 PSRAM support

Postby ESP_Sprite » Sat Jun 03, 2017 12:21 pm

For what it's worth - while we don't have a timeline for it, we also have the idea to add non-flash-cache-based psram access to esp-idf. This would mean that you can fetch data from the psram or write data to psram using a function call, but you cannot directly allocate memory pointers in it or store variables in it. While it won't suffice for all applications, for example audio applications can benefit from it. Because the issues are purely in the cache, this way of accessing it will also be compatible with v0 ESP32s.

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Re: ESP32 PSRAM support

Postby BuddyCasino » Sat Jun 03, 2017 12:33 pm

While it won't suffice for all applications, for example audio applications can benefit from it.

Yeah I'd already be happy to shove some buffers into pSRAM, just like with your ESP8266 MP3 decoder.
Do you think it would be fast enough for SSL buffers, too? What is the speed difference with main sram, disregarding caches?

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Re: ESP32 PSRAM support

Postby rudi ;-) » Sat Jun 03, 2017 3:58 pm

ESP_Sprite wrote:For what it's worth - while we don't have a timeline for it, we also have the idea to add non-flash-cache-based psram access to esp-idf. This would mean that you can fetch data from the psram or write data to psram using a function call, but you cannot directly allocate memory pointers in it or store variables in it. While it won't suffice for all applications, for example audio applications can benefit from it. Because the issues are purely in the cache, this way of accessing it will also be compatible with v0 ESP32s.



ok Jeroen. honest thank you for your effort - i understand now better the things in background.
so i talked to wear leveling and other too in the past - ...

this non-flash-cache-based psram access would help - cause i can not wait - ( you know me )
i try this in the past - but have no access -

i know - we must put all function to the non cache - to IRAM -

one thing i do not understand, perhabs you can help in this way with an Info about,
i know - you are very detailed and you are visionaer - so i ask you for hope to get answers:

in the technical reference there is a picture, that psram share CLK with flash
you know.
Image

we know now, that this picture must be wrong, cause CLK need to separate for psram. and here comes the same confirm
- at first, can you confirm, the picture is wrong?
- does this mean, that only the workaround need this for rev1 or is this gerenally for the psram then?


we know now, that the pins on this picture must be wrong then too ?! ,
cause the pic shows DI, DO, WP and HOLD QIO mode
but in the pSRAM support, we use DI, DO and WP ( mode ? )
this is a diffenet mode -

hold is not named and not use.


i ask for the mode, cause we have 1 bit Input and Output separate or 4 bit I/O common interface
1 bit Input and Output separate means DI, DO right?
and
4 bit I/O common interface means SD_0..SD_3, right?

psram_all.jpg
psram_all.jpg (78.9 KiB) Viewed 718 times


btw XTX sales espressif brandmarked pSRAM - so i think - it is the same

from the future/psram-maloc

To connect the ESP-PSRAM chip to the ESP32, connect the following signals:

    PSRAM /CE (pin 1) - ESP32 GPIO 17
    PSRAM SO (pin 2) - flash DO
    PSRAM SIO[2] (pin 3) - flash WP
    PSRAM SI (pin 5) - flash DI
    PSRAM SCLK (pin 6) - ESP32 GPIO 16
    PSRAM Vcc (pin 8) - ESP32 VCC_SDIO

in which mode the pSRAM then comes to rev1 in this ?
and which mode you would use for the non-flash-cache-based psram access then?


honest honest honest - it is very sad that we got the wrover without an info from espressif ( they knowed that we need psram, cause we bought psram too to the wrovers in same package and ESP32-D2WDQ5 - ) that this wrover are rev0.
i do not believe, that they have this not knowed.

i wished, that here espressif goes opener to the companies for this - I have to digest this sad truth..
and contacted john and stanza with pleased now - for fast sending this beta rev1 wrover that we can work on psram here.
we have no possible way for use/test/show psram on esp32 - this is very sad after 3 years on espressif's products
but this is an other theme.

i know - you gave the tip to can mount wrover to the wrover kits - and that the espressif team do this too.
but what sense make this - if we can not use psram on the modules? -

here i missed the info "but you can't use psram cause this is rev0"
this theme that rev0 does not support psram in this way - is longer knowed in espressif - so i do not understand this tactic.
then we can save time and nerve and we professionals do not need to "Argue about ignorance"



now wrover kit's are back - does this again be wroom-32 rev0 and do not support psram? or are this wrover modules with rev0 and this are not support psram or are this the versions with wrover rev1 ( beta ) ?

i ask cause here the same - wrovers in the spot - with wrover modul and camera connector update, does this be wrover rev1 or again wrover rev0 and do not support psram

It looks very confusing - "I found out ESP32 WROVER KIT,With SRAM Module"

can we use SRAM on it?

hope you understand me now better.

best wishes
rudi ;-)


ps:
now its clearing, psram 1.8, flash 1.8, CLK and CS in the VSDIO domain, and CLK must be separate.

now we need a code sceleton for using this pSRAM as usually SPI RAM Jeroen,
is this possible to test this on this way in a short time ( 1-2 days )
and do the same thing for a test ->
can you help? can you provide a code example to huck up the pSRAM on wrover rev0 SoC'S ?

if i can use the pSRAM on this way for pushing data and read data
this helps - we need not the cache maloc version in this step
( later sure - we need this - but then better wait and use "ESP64" instead ESP32 rev1 with workarounds )


Code: Select all


int ICACHE_FLASH_ATTR spiRamTest() {
   int x;
   int err=0;
   char a[64];
   char b[64];
   char aa, bb;
   for (x=0; x<64; x++) {
      a[x]=x^(x<<2);
      b[x]=0xaa^x;
   }
   spiRamWrite(0x0, a, 64);
   spiRamWrite(0x100, b, 64);

   spiRamRead(0x0, a, 64);
   spiRamRead(0x100, b, 64);
   for (x=0; x<64; x++) {
      aa=x^(x<<2);
      bb=0xaa^x;
      if (aa!=a[x]) {
         err=1;
//         printf("aa: 0x%x != 0x%x\n", aa, a[x]);
      }
      if (bb!=b[x]) {
         err=1;
//         printf("bb: 0x%x != 0x%x\n", bb, b[x]);
      }
   }
   return !err;
}


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rudi ;-)
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Re: ESP32 PSRAM support

Postby rudi ;-) » Sun Jun 04, 2017 12:33 am

wrover_get_started.jpg
wrover_get_started.jpg (71.48 KiB) Viewed 694 times



can it be that now the pins are swapped ? or is this a mistake?

like i sayed, the wrover starting guide says,

"GPIO16 and GPIO17 are used as the CS and clock signal for PSRAM. To ensure
reliable performance, the two GPIOs are not led out."

means

GPIO16 = CS
GPIO17= CLK

but in the future/psram_maloc
there are the pins swapped


To connect the ESP-PSRAM chip to the ESP32, connect the following signals:

    PSRAM /CE (pin 1) - ESP32 GPIO 17
    PSRAM SO (pin 2) - flash DO
    PSRAM SIO[2] (pin 3) - flash WP
    PSRAM SI (pin 5) - flash DI
    PSRAM SCLK (pin 6) - ESP32 GPIO 16
    PSRAM Vcc (pin 8) - ESP32 VCC_SDIO


btw:

the psram code itself speaks the same like the Getting Started Guide

Code: Select all

#define PSRAM_CLK_IO      17
#define PSRAM_CS_IO 16


guys please!
think now its time @espressif to figure this on right way out that we can all right work on it?


very confusing more and more this theme.
....
....

i think i go now "play" bit bang with pSRAM on this way again

_labor_work-1.jpg
_labor_work-1.jpg (143.05 KiB) Viewed 694 times


btw not sure for what we use /WP in pSRAM
this is not mentioned in the pSRAM Datasheet
......
......

PR is here
.....
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ESP_Sprite
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Re: ESP32 PSRAM support

Postby ESP_Sprite » Sun Jun 04, 2017 7:28 am

Please refer to the actual documentation of the specific pinouts, like the relevant documentation of external RAM in esp-idf or the psram code itself, for the pinouts. Sentences like 'GPIO17 and GPIO16 are used as CS and CLK' are only meant to illustrate that these two pins are in use, they are not meant to derive a pinout from (we'd use 'respectively' in that case to indicate there's an 1-to-1 match.)

The WP pin is in use because the PSRAM also allows quad-IO mode, with data going through DI, DO, WP and HOLD at the same time.

The datasheet illustrates the general case for adding an extra RAM chip to the flash bus. In this case, however, because of an incompatibility of the requirements between most flash chips and the specific type of RAM-chip that is the ESP-PSRAM32, we also need a separate clock line.

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Re: ESP32 PSRAM support

Postby rudi ;-) » Sun Jun 04, 2017 9:10 am

ESP_Sprite wrote:Please refer to the actual documentation of the specific pinouts, like the relevant documentation of external RAM in esp-idf or the psram code itself, for the pinouts. Sentences like 'GPIO17 and GPIO16 are used as CS and CLK' are only meant to illustrate that these two pins are in use, they are not meant to derive a pinout from (we'd use 'respectively' in that case to indicate there's an 1-to-1 match.)

The WP pin is in use because the PSRAM also allows quad-IO mode, with data going through DI, DO, WP and HOLD at the same time.

The datasheet illustrates the general case for adding an extra RAM chip to the flash bus. In this case, however, because of an incompatibility of the requirements between most flash chips and the specific type of RAM-chip that is the ESP-PSRAM32, we also need a separate clock line.


"only meant to illustrate"

ok..
thank you.


ok - i will not take the document "wrover kit getting started" for my understand on "illustrate"
i will now speak facts:

https://github.com/espressif/esp-idf/tr ... ram_malloc
the Readme of the future/psram_maloc
speak,
that CE goes to GPIO 17
that SCLK goes to GPIO 16


and in the code of this repo
https://github.com/espressif/esp-idf/bl ... 32/psram.c
on line 50
https://github.com/espressif/esp-idf/bl ... sram.c#L50

Code: Select all

#define PSRAM_CLK_IO 17


on line 51
https://github.com/espressif/esp-idf/bl ... sram.c#L51

Code: Select all

#define PSRAM_CS_IO 16


info about the pin function is swapped - what is right or not right - we do not know, one part must here change.

sory for the hint from me that there must be a wrong part or swapped pins.
it is important to connect the things right,
a clk do pulse the data where the cs pin do select only the device for active or not one time in data action.

i will use the pins in code now. i am happy that the code is open to can read in it - and not be in a binary blob " lib "
like all other libs


pin names
psram
if we use 1-bit mode, means we must know, where pins SI, SO - but no WP pin or HOLD
if we use 4-bit mode, means we must know, where pins S[0] S[1] S[2] S[3] - but no WP pin
WP pin is no data pin
if pin is named as WP pin
then is spoke from Write Protect Pin - no data pin
WP means, "Enables/Disables the Lock-Down function of the status register"

the HOLD pin is the same, there is no data pin with HOLD
HOLD means, "Suspends a serial sequence to the memory without deselecting the device"

if you look in the pSRAM Datasheet, there is no WP or HOLD funtion for this pSRAM Device.
and there is no describtion for WP or/and HOLD funtion to the pSRAM Device.

if you talk from quad-IO mode, "DI, DO, WP and HOLD"
then this is absolutly wrong named jeroen - sry -

quad-IO mode means, S[0]...S[3] as data pins - as input and as output for data
in international technicals there is named sometime SD[0]..SD[3] or SIO[0]..SIO[3] too
but never WP or/and HOLD
this "function names" are not available in quad-IO mode.

please use norm pin names for the 1-4 bit mode on device and document
then there is no missunderstand in pins and pinfuntion.

if i read
SI
SO
WP#
HOLD#
means never quad mode - it is allways in simply SPI Mode
SI = Serial input ( MOSI )
SO = Serial output ( MISO)

MISO means - Master Input / Slave Output
MOSI means - Master Output / Slave Input


if i read ( left side, the right side is for your understand )
SIO[0] .. SI
SIO[1] .. SO
SIO[2] .. WP#
SIO[3] .. HOLD#
means quad mode - and there is no WP# Write Protect or HOLD# HOLD funtion
so never named the pins WP or/and HOLD in a quad-IO-mode cause there is no pin so named and functional used.
there are only data pins for IO
IO means
Input
Output

keep smile! i like you.

rudi
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Re: ESP32 PSRAM support

Postby rudi ;-) » Sun Jun 04, 2017 9:15 am

ESP_Sprite wrote:The WP pin is in use because the PSRAM also allows quad-IO mode, with data going through DI, DO, WP and HOLD at the same time.


btw:
The "HOLD" Pin if you mean SIO[3] is not given in the last Readme, and is not given in the Code as GPIO HOLD#
this pin is missed in the Readme - where we must connect - and usually in the code used from/for SIO[3]


To connect the ESP-PSRAM chip to the ESP32, connect the following signals:

    PSRAM /CE (pin 1) - ESP32 GPIO 17
    PSRAM SO (pin 2) - flash DO
    PSRAM SIO[2] (pin 3) - flash WP
    PSRAM SI (pin 5) - flash DI
    PSRAM SCLK (pin 6) - ESP32 GPIO 16
    PSRAM Vcc (pin 8) - ESP32 VCC_SDIO

PSRAM SIO[3] (pin 7 ) - flash HOLD

is missing in the connect info

and if you read in the pSRAM Datasheet
Fast quad read access and quad write access in SPI mode will use SIO[3:2].
means like i wrote before.

if you not have, here my personal version:
NO WP or NO HOLD


rudi-psram.png
rudi-psram.png (47.52 KiB) Viewed 674 times


again
keep smile - i like you

rudi
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Re: ESP32 PSRAM support

Postby ESP_Sprite » Sun Jun 04, 2017 3:08 pm

Huh, you're right - seems I skipped over pin 7. Thanks for noticing, will fix it as soon as I have time. Same with the code/documentation discrepancy - those should match up, will see which one is wrong.

I can't easily check the code now, but my guess is that WP and HOLD aren't mentioned anywhere in the PSRAM code because they're already set up correctly for the SPI flash. On a flash chip, in the right mode (quad I/O) they *are* actually used as data pins; it's just that quad I/O is a relatively new development, and seemingly the chip manufacturers still only use the old pin names. (See e.g. here, last sentence of 7.3 on page 8.)

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