ESP32 PSRAM support

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rudi ;-)
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Re: ESP32 PSRAM support

Postby rudi ;-) » Sat Jun 10, 2017 9:36 am

ESP_Sprite wrote:Sorry for the short reply, but to be honest we haven't really looked t the D2WD/PSRAM combo that much yet... We will do this in the future, including determining which pins to use.


no problem so i know jeroen.
just in time think over small things that puzzles me
btw:

i know, there is on espressif / private a test case for D2
and the shematic is well knowed for using D2 well

Yes, I've been using one most days as a development device for over a month now. If using esptool.py on the command line or via IDF makefiles, ESP32-D2WD should be fully supported. ....
..
..
My ESP32-D2WD has revision 0 silicon. I don't know what chips you've received, I am guessing also revision 0



but not sure, how it looks and how it can deal with expansion ( pSRAM and so on )
so i ask, is this test case include a possible for later pSRAM testings or was this test case only for esptool and code test.
cause if here at desk things go on and successful i would write that you can test too ( if you can't cause there is no possible test case
it would be sade )

there are given nice test sockets for the QFN and i go on to do this on this way for first steps that we all flexible.
so it would be from interesst for the price for the test case, cause if pSRAM generall not possible on D2 then we know
and we do not build possibles on this test case here and save the money :)

so perhabs the question is greater, does we can use pSRAM on D2 generell.
if this just in time not knowed - no problem ( please feel free to make a short reply "not sure" then is ok )

with this test sockets

CYT009AriesTestSocket.jpg
CYT009AriesTestSocket.jpg (50.12 KiB) Viewed 719 times


or this qfn(32) -> qfn(48) socket on pcb
pcb_socket_qfn_custom.jpg
pcb_socket_qfn_custom.jpg (88.22 KiB) Viewed 719 times


or others

i am flexible - with an pcb it is static.

thank you jeroen

perhabs if there is a new on this D2 theme and pSRAM, i bookmark this theme for append things in this thread.
would be nice, if you can append after new knowledge too here , thank you!

btw
just in time here at desk is starting test 128MiB flash(3.3) and 64MiB pSRAM(3.3) on D0WDQ6 and our testcase.
( MOQ later custom Wrover at espressif if success - )

nice weekend - enjoy it.

best wishes
rudi ;-)
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pmlody
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Joined: Sat Jan 28, 2017 5:02 pm

Re: ESP32 PSRAM support

Postby pmlody » Tue Jun 13, 2017 7:04 am

@rudi
Can you tell mi with psram chip are you using?

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rudi ;-)
Posts: 1083
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Re: ESP32 PSRAM support

Postby rudi ;-) » Tue Jun 13, 2017 9:23 am

pmlody wrote:@rudi
Can you tell mi with psram chip are you using?


@pmlody
just in time the esp-psram32
you can contact sales@espressif.com
( not sure is just in time available but talk to sales )

the second is lyonthek's
32, 64 and latest 128 - but this just in time pending ..cause

1).LY68S3200SL -32Mb 1.8V QPI pSRAM-Mass production Now.
2).LY68S6400SL -64Mb 1.8V QPI pSRAM-Sample Jun/M/2017 and MP Jul./M/2017
3).LY68L6400SL -64Mb 3.3V QPI pSRAM-Sample July/M/2017 and MP Aug./M/2017
4).LY68S1600SL -16Mb 1.8V QPI pSRAM-Sample Sept./M/2017 and MP Oct./M/2017
5).LY68L1600SL -16Mb 1.8V QPI pSRAM-Sample Oct./M/2017 and MP Nov./M/2017
6).LY68L3200SL -32Mb 3.3V QPI pSRAM-Sample Jan./M/2018 and MP Feb./M/2018


hope for the parcel asap.
hope this helps
best wishes
rudi ;-)
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love it, change it or leave it.
-------------------------------------
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WiFive
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Joined: Tue Dec 01, 2015 7:35 am

Re: ESP32 PSRAM support

Postby WiFive » Tue Jun 27, 2017 5:26 am

Any update on when psram branch will be merged into master or vice versa?

ESP_Sprite
Posts: 1033
Joined: Thu Nov 26, 2015 4:08 am

Re: ESP32 PSRAM support

Postby ESP_Sprite » Tue Jun 27, 2017 7:26 am

If any, post 2.1.

WiFive
Posts: 1020
Joined: Tue Dec 01, 2015 7:35 am

Re: ESP32 PSRAM support

Postby WiFive » Tue Jun 27, 2017 6:35 pm

ESP_Sprite wrote:If any, post 2.1.


Ok so how to look at esp32 rev1 SPIRAM support in IDF from a product planning standpoint? Will it always be second class citizen in terms of IDF updates, separate branch? Do you suggest to consider waiting for "ESP-NEXT" chip for fixed SPIRAM and first class IDF support?

ESP_Sprite
Posts: 1033
Joined: Thu Nov 26, 2015 4:08 am

Re: ESP32 PSRAM support

Postby ESP_Sprite » Wed Jun 28, 2017 4:25 am

Maybe my previous respons was a bit too short, as well as the 'if any' bit too easy to misread; my apologies. Let me correct that: Essentially no, the SPI-PSRAM support will be merged in the main ESP-IDF, but at the time I posted the branch here, the 2.1 release was too close to safely put it in there. We will try to merge it post-2.1, but we're not 100% sure of the timeframe; it'll probably get in there before 3.0 is released but it's not 100% certain.

Wrt hardware support: For the ESP32 dual-core version, while we do have ideas for the future, at the moment we aren't working on any metal revisions to fix the issues that need a compiler workaround. The ESP32 single-core revision however will have fixed SPI RAM support and should be able to run without compiler workarounds.

WiFive
Posts: 1020
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Re: ESP32 PSRAM support

Postby WiFive » Wed Jun 28, 2017 4:59 am

OK thanks for clarifying. Any info on rev1+SPIRAM hardware and toolchain in unit testing and CI flow?

Would be nice to have firmware ready for production when wrover ships.

Would also be really nice to know when to expect S0WD, 8689, and the new chip.

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rudi ;-)
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Re: ESP32 PSRAM support

Postby rudi ;-) » Wed Jul 05, 2017 8:02 am

@ESP_Stanza
@johnlee
@ESP_igrr

please help to this never ending story now
we need now a detailed help - and the wrover shematic with HDK/BOM now for compare.

i have an espressif wrover modul with time stamp 502016 on the SOC and it is rev0
i wrote a simple firmware with testings and psram as spi ram for this and tested successfull.

FYI: i have the rev 1 too, and tested the same firmware successful, so i am sure, the fw ( code ) is ok

now we have a testmodul ( again soc rev 0 ) with lyonteks 32 MBit psram 1.8 and a 64 MBit flash.

the bootloader is booting and the first testings for test the flash is ok, it is the same code on firmware!
the SoC load the bootloader from SPI Flash well and start it
it wait now for user input for echo the inputs from the uart
we can communicate with it and to this "step" is all ok.
this let us know - the flash works - cause the soc can handle and read/save from and on the 64MBit flash
.. all ok to this step:

Code: Select all

rst:0x1 (POWERON_RESET),boot:0x33 (SPI_FAST_FLASH_BOOT)
ets Jun  8 2016 00:22:57


rst:0x10 (RTCWDT_RTC_RESET),boot:0x33 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0008,len:4
load:0x3fff000c,len:4400
ho 0 tail 12 room 4
load:0x40078000,len:12348
load:0x40080000,len:268
entry 0x40080034
[0;32mI (47) boot: ALB-ESP32x64-IDF v2.0-rc1-891-g9faf9c9 2nd stage bootloader[0m
[0;32mI (47) boot: compile time 14:32:34
TEST-SOP-OK?
:T
:E
:S
:T
:


the next step is then to run the rest code and load the app code.
in this steps we test the psram

Code: Select all


[0;32mI (10807) boot: Enabling RNG early entropy source...[0m
[0;32mI (10807) boot: SPI Speed      : 40MHz[0m
[0;32mI (10807) boot: SPI Mode       : DIO[0m
[0;32mI (10820) boot: SPI Flash Size : 8MB[0m
[0;32mI (10834) boot: Partition Table:[0m
[0;32mI (10846) boot: ## Label            Usage          Type ST Offset   Length[0m
[0;32mI (10869) boot:  0 nvs              WiFi data        01 02 00009000 00006000[0m
[0;32mI (10893) boot:  1 phy_init         RF data          01 01 0000f000 00001000[0m
[0;32mI (10916) boot:  2 factory          factory app      00 00 00010000 00100000[0m
[0;32mI (10940) boot: End of partition table[0m
[0;32mI (10954) boot: Disabling RNG early entropy source...[0m
[0;32mI (10971) boot: Loading app partition at offset 00010000[0m
[0;32mI (11510) boot: segment 0: paddr=0x00010018 vaddr=0x00000000 size=0x0ffe8 ( 65512) [0m
[0;32mI (11510) boot: segment 1: paddr=0x00020008 vaddr=0x3f400010 size=0x06f98 ( 28568) map[0m
[0;32mI (11527) boot: segment 2: paddr=0x00026fa8 vaddr=0x3ffb0000 size=0x022f4 (  8948) load[0m
[0;32mI (11558) boot: segment 3: paddr=0x000292a4 vaddr=0x40080000 size=0x00400 (  1024) load[0m
[0;32mI (11581) boot: segment 4: paddr=0x000296ac vaddr=0x40080400 size=0x14858 ( 84056) load[0m
[0;32mI (11648) boot: segment 5: paddr=0x0003df0c vaddr=0x400c0000 size=0x00000 (     0) load[0m
[0;32mI (11649) boot: segment 6: paddr=0x0003df14 vaddr=0x00000000 size=0x020f4 (  8436) [0m
[0;32mI (11667) boot: segment 7: paddr=0x00040010 vaddr=0x400d0018 size=0x2ab84 (174980) map[0m



and there is then the GURU:

Code: Select all


Guru Meditation Error of type IllegalInstruction occurred on core  0. Exception was unhandled.
Register dump:
PC      : 0x400d1b60  PS      : 0x00060530  A0      : 0x800824d0  A1      : 0x3ffe3be0 
A2      : 0x3ffe3c30  A3      : 0x00000a00  A4      : 0x3ff4904c  A5      : 0x00000000 
A6      : 0x00000001  A7      : 0x00000001  A8      : 0x00000000  A9      : 0x3ffe3b90 
A10     : 0x00000001  A11     : 0x00000000  A12     : 0x00000034  A13     : 0x00000000 
A14     : 0x000008ff  A15     : 0x00000004  SAR     : 0x00000017  EXCCAUSE: 0x00000000 
EXCVADDR: 0x00000000  LBEG    : 0x40094a40  LEND    : 0x40094a6e  LCOUNT  : 0xffffffff 


Backtrace: 0x400d1b60:0x3ffe3be0 0x400824d0:0x3ffe3c30 0x40080f0e:0x3ffe3c60 0x40078855:0x3ffe3ca0 0x40078a7c:0x3ffe3cd0 0x40079110:0x3ffe3d50 0x40080109:0x3ffe3e70 0x40007c34:0x3ffe3eb0 0x40000740:0x3ffe3f20

Rebooting...
ets Jun  8 2016 00:22:57

Rebooting...
ets Jun  8 2016 00:22:57


rst:0xc (SW_CPU_RESET),boot:0x33 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0008,len:4
load:0xcf3f00c3,len:4195532
1162 mmu set 00010000, pos 00010000
1162 mmu set 00020000, pos 00020000
1162 mmu set 00030000, pos 00030000
1162 mmu set 00040000, pos 00040000
1162 mmu set 00050000, pos 00050000
1162 mmu set 00060000, pos 00060000
1162 mmu set 00070000, pos 00070000
1162 mmu set 00080000, pos 00080000
1162 mmu set 00090000, pos 00090000
1162 mmu set 000a0000, pos 000a0000
1162 mmu set 000b0000, pos 000b0000
1162 mmu set 000c0000, pos 000c0000
1162 mmu set 000d0000, pos 000d0000
1162 mmu set 000e0000, pos 000e0000
1162 mmu set 000f0000, pos 000f0000
1162 mmu set 00100000, pos 00100000
1162 mmu set 00110000, pos 00110000
1162 mmu set 00120000, pos 00120000
1162 mmu set 00130000, pos 00130000
1162 mmu set 00140000, pos 00140000
1162 mmu set 00150000, pos 00150000
1162 mmu set 00160000, pos 00160000
1162 mmu set 00170000, pos 00170000
1162 mmu set 00180000, pos 00180000
1162 mmu set 00190000, pos 00190000
ets Jun  8 2016 00:22:57


rst:0x10 (RTCWDT_RTC_RESET),boot:0x33 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0008,len:4
load:0x3fff000c,len:4400
ho 0 tail 12 room 4
load:0x40078000,len:12348
load:0x40080000,len:268
entry 0x40080034
[0;32mI (47) boot: ALB-ESP32x64-IDF v2.0-rc1-891-g9faf9c9 2nd stage bootloader[0m
[0;32mI (47) boot: compile time 14:32:34[0m
TEST-SOP-OK?









an other test and log:

Code: Select all


rst:0x1 (POWERON_RESET),boot:0x33 (SPI_FAST_FLASH_BOOT)
ets Jun  8 2016 00:22:57


rst:0x10 (RTCWDT_RTC_RESET),boot:0x33 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0008,len:4
load:0x3fff000c,len:4400
ho 0 tail 12 room 4
load:0x40078000,len:12348
load:0x40080000,len:268
entry 0x40080034
[0;32mI (47) boot: ALB-ESP32x64-IDF v2.0-rc1-891-g9faf9c9 2nd stage bootloader[0m
[0;32mI (47) boot: compile time 14:32:34[0m
TEST-SOP-OK?
:O
:K
:


[0;32mI (128497) boot: Enabling RNG early entropy source...[0m
[0;32mI (128497) boot: SPI Speed      : 40MHz[0m
[0;32mI (128498) boot: SPI Mode       : DIO[0m
[0;32mI (128510) boot: SPI Flash Size : 8MB[0m
[0;32mI (128523) boot: Partition Table:[0m
[0;32mI (128535) boot: ## Label            Usage          Type ST Offset   Length[0m
[0;32mI (128559) boot:  0 nvs              WiFi data        01 02 00009000 00006000[0m
[0;32mI (128583) boot:  1 phy_init         RF data          01 01 0000f000 00001000[0m
[0;32mI (128607) boot:  2 factory          factory app      00 00 00010000 00100000[0m
[0;32mI (128631) boot: End of partition table[0m
[0;32mI (128645) boot: Disabling RNG early entropy source...[0m
[0;32mI (128663) boot: Loading app partition at offset 00010000[0m
[0;32mI (129201) boot: segment 0: paddr=0x00010018 vaddr=0x00000000 size=0x0ffe8 ( 65512) [0m
[0;32mI (129202) boot: segment 1: paddr=0x00020008 vaddr=0x3f400010 size=0x06f98 ( 28568) map[0m
[0;32mI (129219) boot: segment 2: paddr=0x00026fa8 vaddr=0x3ffb0000 size=0x022f4 (  8948) load[0m
[0;32mI (129250) boot: segment 3: paddr=0x000292a4 vaddr=0x40080000 size=0x00400 (  1024) load[0m
[0;32mI (129274) boot: segment 4: paddr=0x000296ac vaddr=0x40080400 size=0x14858 ( 84056) load[0m
[0;32mI (129341) boot: segment 5: paddr=0x0003df0c vaddr=0x400c0000 size=0x00000 (     0) load[0m
[0;32mI (129342) boot: segment 6: paddr=0x0003df14 vaddr=0x00000000 size=0x020f4 (  8436) [0m
[0;32mI (129360) boot: segment 7: paddr=0x00040010 vaddr=0x400d0018 size=0x2ab84 (174980) map[0m
Guru Meditation Error of type IllegalInstruction occurred on core  0. Exception was unhandled.
Register dump:
PC      : 0x400d1b60  PS      : 0x00060530  A0      : 0x800824d0  A1      : 0x3ffe3be0 
A2      : 0x3ffe3c30  A3      : 0x00000a00  A4      : 0x3ff4904c  A5      : 0x00000000 
A6      : 0x00000001  A7      : 0x00000001  A8      : 0x00000000  A9      : 0x3ffe3b90 
A10     : 0x00000001  A11     : 0x00000000  A12     : 0x00000034  A13     : 0x00000000 
A14     : 0x000008ff  A15     : 0x00000004  SAR     : 0x00000017  EXCCAUSE: 0x00000000 
EXCVADDR: 0x00000000  LBEG    : 0x40094a40  LEND    : 0x40094a6e  LCOUNT  : 0xffffffff 


Backtrace: 0x400d1b60:0x3ffe3be0 0x400824d0:0x3ffe3c30 0x40080f0e:0x3ffe3c60 0x40078855:0x3ffe3ca0 0x40078a7c:0x3ffe3cd0 0x40079110:0x3ffe3d50 0x40080109:0x3ffe3e70 0x40007c34:0x3ffe3eb0 0x40000740:0x3ffe3f20


Rebooting...
ets Jun  8 2016 00:22:57


rst:0xc (SW_CPU_RESET),boot:0x33 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0008,len:4
load:0xcf3f00c3,len:4195532
1162 mmu set 00010000, pos 00010000
1162 mmu set 00020000, pos 00020000
1162 mmu set 00030000, pos 00030000
1162 mmu set 00040000, pos 00040000
1162 mmu set 00050000, pos 00050000
1162 mmu set 00060000, pos 00060000
1162 mmu set 00070000, pos 00070000
1162 mmu set 00080000, pos 00080000
1162 mmu set 00090000, pos 00090000
1162 mmu set 000a0000, pos 000a0000
1162 mmu set 000b0000, pos 000b0000
1162 mmu set 000c0000, pos 000c0000
1162 mmu set 000d0000, pos 000d0000
1162 mmu set 000e0000, pos 000e0000
1162 mmu set 000f0000, pos 000f0000
1162 mmu set 00100000, pos 00100000
1162 mmu set 00110000, pos 00110000
1162 mmu set 00120000, pos 00120000
1162 mmu set 00130000, pos 00130000
1162 mmu set 00140000, pos 00140000
1162 mmu set 00150000, pos 00150000
1162 mmu set 00160000, pos 00160000
1162 mmu set 00170000, pos 00170000
1162 mmu set 00180000, pos 00180000
1162 mmu set 00190000, pos 00190000
ets Jun  8 2016 00:22:57




an other test without the SOP Test ( Echo test ) and log

Code: Select all


rst:0x10 (RTCWDT_RTC_RESET),boot:0x33 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0008,len:4
load:0x3fff000c,len:4396
load:0x40078000,len:12180
load:0x40080000,len:268
entry 0x40080034
[0;32mI (44) boot: ESP32x-IDF v2.0-rc1-891-g9faf9c9 2nd stage bootloader[0m
[0;32mI (45) boot: compile time 13:29:45[0m
[0;32mI (45) boot: Enabling RNG early entropy source...[0m
[0;32mI (63) boot: SPI Speed      : 40MHz[0m
[0;32mI (76) boot: SPI Mode       : DIO[0m
[0;32mI (88) boot: SPI Flash Size : 8MB[0m
[0;32mI (100) boot: Partition Table:[0m
[0;32mI (112) boot: ## Label            Usage          Type ST Offset   Length[0m
[0;32mI (135) boot:  0 nvs              WiFi data        01 02 00009000 00006000[0m
[0;32mI (158) boot:  1 phy_init         RF data          01 01 0000f000 00001000[0m
[0;32mI (181) boot:  2 factory          factory app      00 00 00010000 00100000[0m
[0;32mI (204) boot: End of partition table[0m
[0;32mI (217) boot: Disabling RNG early entropy source...[0m
[0;32mI (234) boot: Loading app partition at offset 00010000[0m
[0;32mI (772) boot: segment 0: paddr=0x00010018 vaddr=0x00000000 size=0x0ffe8 ( 65512) [0m
[0;32mI (773) boot: segment 1: paddr=0x00020008 vaddr=0x3f400010 size=0x06f98 ( 28568) map[0m
[0;32mI (789) boot: segment 2: paddr=0x00026fa8 vaddr=0x3ffb0000 size=0x022f4 (  8948) load[0m
[0;32mI (819) boot: segment 3: paddr=0x000292a4 vaddr=0x40080000 size=0x00400 (  1024) load[0m
[0;32mI (842) boot: segment 4: paddr=0x000296ac vaddr=0x40080400 size=0x14858 ( 84056) load[0m
[0;32mI (907) boot: segment 5: paddr=0x0003df0c vaddr=0x400c0000 size=0x00000 (     0) load[0m
[0;32mI (908) boot: segment 6: paddr=0x0003df14 vaddr=0x00000000 size=0x020f4 (  8436) [0m
[0;32mI (925) boot: segment 7: paddr=0x00040010 vaddr=0x400d0018 size=0x2ab84 (174980) map[0m
Guru Meditation Error of type IllegalInstruction occurred on core  0. Exception was unhandled.
Register dump:
PC      : 0x400d1b60  PS      : 0x00060530  A0      : 0x800824d0  A1      : 0x3ffe3be0 
A2      : 0x3ffe3c30  A3      : 0x00000a00  A4      : 0x3ff4904c  A5      : 0x00000000 
A6      : 0x00000001  A7      : 0x00000001  A8      : 0x00000000  A9      : 0x3ffe3b90 
A10     : 0x00000001  A11     : 0x00000000  A12     : 0x00000034  A13     : 0x00000000 
A14     : 0x000008ff  A15     : 0x00000004  SAR     : 0x00000017  EXCCAUSE: 0x00000000 
EXCVADDR: 0x00000000  LBEG    : 0x40094a40  LEND    : 0x40094a6e  LCOUNT  : 0xffffffff 


Backtrace: 0x400d1b60:0x3ffe3be0 0x400824d0:0x3ffe3c30 0x40080f0e:0x3ffe3c60 0x4007884d:0x3ffe3ca0 0x40078a74:0x3ffe3cd0 0x40079068:0x3ffe3d50 0x40080109:0x3ffe3e70 0x40007c34:0x3ffe3eb0 0x40000740:0x3ffe3f20


Rebooting...
ets Jun  8 2016 00:22:57


rst:0xc (SW_CPU_RESET),boot:0x33 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0008,len:4
load:0xcf3f00c3,len:4195531
1162 mmu set 00010000, pos 00010000
1162 mmu set 00020000, pos 00020000
1162 mmu set 00030000, pos 00030000
1162 mmu set 00040000, pos 00040000
1162 mmu set 00050000, pos 00050000
1162 mmu set 00060000, pos 00060000
1162 mmu set 00070000, pos 00070000
1162 mmu set 00080000, pos 00080000
1162 mmu set 00090000, pos 00090000
1162 mmu set 000a0000, pos 000a0000
1162 mmu set 000b0000, pos 000b0000
1162 mmu set 000c0000, pos 000c0000
1162 mmu set 000d0000, pos 000d0000
1162 mmu set 000e0000, pos 000e0000
1162 mmu set 000f0000, pos 000f0000
1162 mmu set 00100000, pos 00100000
1162 mmu set 00110000, pos 00110000
1162 mmu set 00120000, pos 00120000
1162 mmu set 00130000, pos 00130000
1162 mmu set 00140000, pos 00140000
1162 mmu set 00150000, pos 00150000
1162 mmu set 00160000, pos 00160000
1162 mmu set 00170000, pos 00170000
1162 mmu set 00180000, pos 00180000
1162 mmu set 00190000, pos 00190000
ets Jun  8 2016 00:22:57



info: HDK
Bootstrap pin MTDI is pulled up to VDD33
SPI Flash share Data pins with PSRAM
PSRAM #CE is pulled up to VDD_SDIO and is connected to GPIO16
PSRAM SCK is connected to GPIO17

Q: why this exampe run on Wrover 32MBit_1.8/32MBit_1.8 modul ( SoC Rev 0 )
but not on the custom 64MBit_wide/32MBit_1.8 ( SoC Rev 0 )

Q: the 64MBit is wide flash ( 1.8 .. 3.6 V ) and works with 1.8 and 3.3 - is there a problem with 1.8 driven wide flash and combine 1.8 psram?

Q: we use Lyontek PSRAM, is there a magic key for psram ( ESP-PSRAM32 ) ID and if this not match the PSRAM is not supported?

Q: is there a hidden/not knowed detail on HDK that we not know? ( missing the edited wrover shematic file - can u post now ? )

Q: we need the HDK wrover shematic with BOM like the WROOM32 modul.

best wishes
rudi ;-)


edit1:
and sure:
here is the shematic we use :

bootstrap pulled up:

pulled_up_MTDI.jpg
pulled_up_MTDI.jpg (51.98 KiB) Viewed 457 times




flash and psram

flash_with_psram.jpg
flash_with_psram.jpg (84.59 KiB) Viewed 457 times


now -
we need your shematic and info what we do wrong here.

edit2:
we work with cadence , eagle, kicad so there is no problem to import yours.

edit3:
FYI the name of PSRAM in Shematic is placeholder only ( it is named as 64 Mbit version )
we use 32MBit version on the Modul for the testings -
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love it, change it or leave it.
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ESP_igrr
Posts: 784
Joined: Tue Dec 01, 2015 8:37 am

Re: ESP32 PSRAM support

Postby ESP_igrr » Wed Jul 05, 2017 8:28 am

Rudi,
Can you use idf-monitor (make monitor) when capturing log output? That tool will decode backtraces printed by the panic handler into source code file names and line numbers, which will make it easier to figure something out from the logs.

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