Automatic light sleep and gpio wakeup messes up vTaskDelay

frini37
Posts: 2
Joined: Sun Jul 25, 2021 12:57 pm

Automatic light sleep and gpio wakeup messes up vTaskDelay

Postby frini37 » Sun Jul 25, 2021 2:07 pm

Hi All,
I am working with automatic power management and wakeup form GPIO, and I am facing a problems with vTaskDelay. I have narrowed it to the following code :
  1. #include <stdio.h>
  2. #include "freertos/FreeRTOS.h"
  3. #include "freertos/task.h"
  4. #include "driver/gpio.h"
  5. #include "esp_sleep.h"
  6. #include "esp_pm.h"
  7. #include <sys/unistd.h>
  8.  
  9. void app_main(void)
  10. {
  11.     /* POWER */
  12.     esp_sleep_pd_config(ESP_PD_DOMAIN_VDDSDIO, ESP_PD_OPTION_ON);
  13.  
  14.     gpio_config_t io_conf;
  15.     //disable interrupt
  16.     io_conf.intr_type = GPIO_PIN_INTR_DISABLE;
  17.     //set as output mode
  18.     io_conf.mode = GPIO_MODE_INPUT;
  19.     //bit mask of the pins that you want to set,e.g.GPIO18/19
  20.     io_conf.pin_bit_mask = GPIO_SEL_36;
  21.     //disable pull-down mode
  22.     io_conf.pull_down_en = 1;
  23.     //disable pull-up mode
  24.     io_conf.pull_up_en = 0;
  25.     //configure GPIO with the given settings
  26.     gpio_config(&io_conf);
  27.  
  28.     ESP_ERROR_CHECK(gpio_wakeup_enable(GPIO_NUM_36, GPIO_INTR_HIGH_LEVEL));
  29.     ESP_ERROR_CHECK(esp_sleep_enable_gpio_wakeup());
  30.  
  31. #if CONFIG_PM_ENABLE
  32.     // Configure dynamic frequency scaling:
  33.     // maximum and minimum frequencies are set in sdkconfig,
  34.     // automatic light sleep is enabled if tickless idle support is enabled.
  35.     esp_pm_config_esp32_t pm_config = {.max_freq_mhz = CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ,
  36.                                        .min_freq_mhz = CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ,
  37. #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
  38.                                        .light_sleep_enable = true,
  39. #endif
  40.     };
  41.     ESP_ERROR_CHECK(esp_pm_configure(&pm_config));
  42. #endif // CONFIG_PM_ENABLE
  43.  
  44.     while (1)
  45.     {
  46.         printf("Input pin %d\n", gpio_get_level(GPIO_NUM_36));
  47.         fflush(stdout);
  48.         fsync(fileno(stdout));
  49.         vTaskDelay(1000 / portTICK_PERIOD_MS);
  50.     }
  51. }
In the SDK config I have enabled :
1. Support for power management
2. Tickless idle support

And connected pin 36 to a square wave about 10sec low and 5sec high.
But when the pin is high and the chip is not sleeping according to current measurement, the vTaskDelay intervals are not constant and are higher than 1 sec (some times up to 2sec delay instead of 1 sec).

Does any one have a clue why this is happening ? I am quite lost here....

I get the following output, and the times and delta times are printed by the terminal application -YAT (not from the ESP32):
(16:56:27.079) (0.371) ets Jun 8 2016 00:22:57
(16:56:27.079) (0.000)
(16:56:27.079) (0.000) rst:0x1 (POWERON_RESET),boot:0x1b (SPI_FAST_FLASH_BOOT)
(16:56:27.096) (0.017) configsip: 0, SPIWP:0xee
(16:56:27.096) (0.000) clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
(16:56:27.096) (0.000) mode:DIO, clock div:2
(16:56:27.096) (0.000) load:0x3fff0030,len:6984
(16:56:27.111) (0.015) load:0x40078000,len:14292
(16:56:27.111) (0.000) load:0x40080400,len:3688
(16:56:27.111) (0.000) entry 0x40080678
(16:56:27.111) (0.000) <ESC>[0;32mI (27) boot: ESP-IDF v4.3-dirty 2nd stage bootloader<ESC>[0m
(16:56:27.124) (0.013) <ESC>[0;32mI (27) boot: compile time 16:33:13<ESC>[0m
(16:56:27.124) (0.000) <ESC>[0;32mI (27) boot: chip revision: 1<ESC>[0m
(16:56:27.124) (0.000) <ESC>[0;32mI (30) boot_comm: chip revision: 1, min. bootloader chip revision: 0<ESC>[0m
(16:56:27.140) (0.015) <ESC>[0;32mI (37) boot.esp32: SPI Speed : 40MHz<ESC>[0m
(16:56:27.140) (0.000) <ESC>[0;32mI (42) boot.esp32: SPI Mode : DIO<ESC>[0m
(16:56:27.140) (0.000) <ESC>[0;32mI (46) boot.esp32: SPI Flash Size : 16MB<ESC>[0m
(16:56:27.140) (0.000) <ESC>[0;32mI (51) boot: Enabling RNG early entropy source...<ESC>[0m
(16:56:27.160) (0.019) <ESC>[0;32mI (56) boot: Partition Table:<ESC>[0m
(16:56:27.160) (0.000) <ESC>[0;32mI (60) boot: ## Label Usage Type ST Offset Length<ESC>[0m
(16:56:27.160) (0.000) <ESC>[0;32mI (67) boot: 0 nvs WiFi data 01 02 00009000 00006000<ESC>[0m
(16:56:27.177) (0.016) <ESC>[0;32mI (75) boot: 1 phy_init RF data 01 01 0000f000 00001000<ESC>[0m
(16:56:27.177) (0.000) <ESC>[0;32mI (82) boot: 2 factory factory app 00 00 00010000 00100000<ESC>[0m
(16:56:27.194) (0.016) <ESC>[0;32mI (90) boot: End of partition table<ESC>[0m
(16:56:27.194) (0.000) <ESC>[0;32mI (94) boot_comm: chip revision: 1, min. application chip revision: 0<ESC>[0m
(16:56:27.194) (0.000) <ESC>[0;32mI (101) esp_image: segment 0: paddr=00010020 vaddr=3f400020 size=07e74h ( 32372) map<ESC>[0m
(16:56:27.213) (0.019) <ESC>[0;32mI (122) esp_image: segment 1: paddr=00017e9c vaddr=3ffb0000 size=02958h ( 10584) load<ESC>[0m
(16:56:27.213) (0.000) <ESC>[0;32mI (126) esp_image: segment 2: paddr=0001a7fc vaddr=40080000 size=0581ch ( 22556) load<ESC>[0m
(16:56:27.246) (0.033) <ESC>[0;32mI (138) esp_image: segment 3: paddr=00020020 vaddr=400d0020 size=1529ch ( 86684) map<ESC>[0m
(16:56:27.262) (0.015) <ESC>[0;32mI (171) esp_image: segment 4: paddr=000352c4 vaddr=4008581c size=06474h ( 25716) load<ESC>[0m
(16:56:27.262) (0.000) <ESC>[0;32mI (182) esp_image: segment 5: paddr=0003b740 vaddr=50000000 size=00010h ( 16) load<ESC>[0m
(16:56:27.282) (0.020) <ESC>[0;32mI (189) boot: Loaded app from partition at offset 0x10000<ESC>[0m
(16:56:27.282) (0.000) <ESC>[0;32mI (189) boot: Disabling RNG early entropy source...<ESC>[0m
(16:56:27.282) (0.000) <ESC>[0;32mI (202) cpu_start: Pro cpu up.<ESC>[0m
(16:56:27.299) (0.016) <ESC>[0;32mI (203) cpu_start: Starting app cpu, entry point is 0x40081144<ESC>[0m
(16:56:27.299) (0.000) <ESC>[0;32mI (0) cpu_start: App cpu up.<ESC>[0m
(16:56:27.299) (0.000) <ESC>[0;32mI (217) cpu_start: Pro cpu start user code<ESC>[0m
(16:56:27.317) (0.018) <ESC>[0;32mI (217) cpu_start: cpu freq: 160000000<ESC>[0m
(16:56:27.317) (0.000) <ESC>[0;32mI (217) cpu_start: Application information:<ESC>[0m
(16:56:27.317) (0.000) <ESC>[0;32mI (221) cpu_start: Project name: blink<ESC>[0m
(16:56:27.317) (0.000) <ESC>[0;32mI (226) cpu_start: App version: 1<ESC>[0m
(16:56:27.338) (0.020) <ESC>[0;32mI (231) cpu_start: Compile time: Jul 25 2021 16:39:45<ESC>[0m
(16:56:27.338) (0.000) <ESC>[0;32mI (237) cpu_start: ELF file SHA256: ccfc48af54591595...<ESC>[0m
(16:56:27.338) (0.000) <ESC>[0;32mI (243) cpu_start: ESP-IDF: v4.3-dirty<ESC>[0m
(16:56:27.338) (0.000) <ESC>[0;32mI (248) heap_init: Initializing. RAM available for dynamic allocation:<ESC>[0m
(16:56:27.356) (0.017) <ESC>[0;32mI (255) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAM<ESC>[0m
(16:56:27.356) (0.000) <ESC>[0;32mI (261) heap_init: At 3FFB31F8 len 0002CE08 (179 KiB): DRAM<ESC>[0m
(16:56:27.356) (0.000) <ESC>[0;32mI (267) heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAM<ESC>[0m
(16:56:27.373) (0.017) <ESC>[0;32mI (274) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM<ESC>[0m
(16:56:27.373) (0.000) <ESC>[0;32mI (280) heap_init: At 4008BC90 len 00014370 (80 KiB): IRAM<ESC>[0m
(16:56:27.392) (0.019) <ESC>[0;32mI (287) spi_flash: detected chip: generic<ESC>[0m
(16:56:27.392) (0.000) <ESC>[0;32mI (291) spi_flash: flash io: dio<ESC>[0m
(16:56:27.392) (0.000) <ESC>[0;32mI (307) cpu_start: Starting scheduler on PRO CPU.<ESC>[0m
(16:56:27.392) (0.000) <ESC>[0;32mI (0) cpu_start: Starting scheduler on APP CPU.<ESC>[0m
(16:56:27.416) (0.024) <ESC>[0;32mI (308) gpio: GPIO[36]| InputEn: 1| OutputEn: 0| OpenDrain: 0| Pullup: 0| Pulldown: 1| Intr:0 <ESC>[0m
(16:56:27.416) (0.000) <ESC>[0;32mI (318) pm: Frequency switching config: CPU_MAX: 160, APB_MAX: 160, APB_MIN: 160, Light sleep: ENABLED<ESC>[0m
(16:56:27.416) (0.000) Input pin 0
(16:56:28.418) (1.001) Input pin 0
(16:56:29.420) (1.002) Input pin 0
(16:56:30.423) (1.002) Input pin 0
(16:56:31.796) (1.373) Input pin 1
(16:56:33.474) (1.677) Input pin 1
(16:56:35.152) (1.678) Input pin 1

(16:56:36.214) (1.061) Input pin 0
(16:56:37.216) (1.001) Input pin 0
(16:56:38.220) (1.004) Input pin 0
(16:56:39.222) (1.001) Input pin 0
(16:56:40.223) (1.001) Input pin 0
(16:56:41.226) (1.002) Input pin 0
(16:56:42.229) (1.002) Input pin 0
(16:56:43.230) (1.001) Input pin 0
(16:56:44.233) (1.002) Input pin 0
(16:56:45.235) (1.002) Input pin 0
(16:56:46.884) (1.649) Input pin 1
(16:56:48.583) (1.699) Input pin 1
(16:56:50.080) (1.497) Input pin 0

(16:56:51.082) (1.002) Input pin 0
(16:56:52.084) (1.001) Input pin 0
(16:56:53.086) (1.001) Input pin 0
(16:56:54.089) (1.002) Input pin 0
(16:56:55.091) (1.002) Input pin 0
(16:56:56.093) (1.002) Input pin 0
(16:56:57.095) (1.001) Input pin 0
(16:56:58.096) (1.001) Input pin 0
(16:56:59.098) (1.001) Input pin 0
(16:57:00.138) (1.040) Input pin 1
(16:57:01.285) (1.146) Input pin 1
(16:57:02.433) (1.148) Input pin 1
(16:57:03.581) (1.147) Input pin 1

(16:57:04.664) (1.082) Input pin 0
(16:57:05.667) (1.003) Input pin 0
(16:57:06.669) (1.002) Input pin 0
(16:57:07.672) (1.002) Input pin 0
(16:57:08.673) (1.001) Input pin 0
(16:57:09.676) (1.002) Input pin 0
(16:57:10.678) (1.001) Input pin 0
(16:57:11.680) (1.002) Input pin 0

frini37
Posts: 2
Joined: Sun Jul 25, 2021 12:57 pm

Re: Automatic light sleep and gpio wakeup messes up vTaskDelay

Postby frini37 » Wed Jul 28, 2021 8:27 am

I have found the issue. I had a problem with the ground signal between the two boards which caused the GPIO to be unstable.

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