IllegalInstruction when UART ISR triggers during SPI FLASH erase/write

sphudson
Posts: 3
Joined: Fri Sep 24, 2021 4:17 pm

IllegalInstruction when UART ISR triggers during SPI FLASH erase/write

Postby sphudson » Fri Sep 24, 2021 5:41 pm

Hello,

This issue has been reported previously, but there is never any firm/solid solution from what I can tell.

Using IDF 4.3.1 and an ESP32-WROVER-B module.

I am running the UART out of IRAM (RS-485 half duplex mode) and am using SPI FLASH to store some application configuration data in a partition (FATFS is also used and the same issue occurs during a file write, which causes the FAT to get corrupted).

I am running into an IllegalInstruction exception, when the UART ISR executes while a SPI FLASH erase/write operation is occurring. It also sometimes crashes with an "Cache disabled but cached memory region access" error. The backtrace looks the same for both errors. This is usually caused by code in flash being accessed during the SPI FLASH erase/write operation.

Below is the monitor dump. A core dump doesn't seem provide anymore insight than the regular backtrace.

My SDKCONFIG file is attached.

I'm wondering if anyone can provide me with some further insights into how to resolve this issue in a practical manner. I don't think I can guarantee that all code that is subsequently invoked from the UART ISR will also be located in IRAM.

Everything works fine, of course, if UART is executed out of flash. However, the de-assertion of the RS485 RTS signal can get extended if a flash erase/write operation is in progress. This causes the RS485 remote device's response to get clobbered or lost since the ESP32 is driving the bus.

Our main RS485 requirement here is that RTS needs to be de-asserted immediately after the last byte is transmitted to allow the remote device to respond back without delay.

One option is, at the application level, run the UART from flash and disable calling uart_write_bytes() during SPI FLASH erases/writes (this would also include ensuring that the transmission is complete and RTS is de-asserted before allowing the SPI FLASH erase/writes to commence).

Any other ideas/insights?

Thanks


=============
Re-enable cpu cache.
Guru Meditation Error: Core 1 panic'ed (IllegalInstruction). Exception was unhandled.
Memory dump at 0x400d5764: fffa060c 90008136 63d00063
0x400d5764: soc_get_available_memory_regions at C:/Users/xxxxxxx/Desktop/esp-idf/components/soc/memory_layout_utils.c:175 (discriminator 3)

Core 1 register dump:
PC : 0x400d576a PS : 0x00060033 A0 : 0x800951cb A1 : 0x3ffbe980
0x400d576a: compare_and_set_extram at C:/Users/xxxxxxx/Desktop/esp-idf/components/esp_hw_support/compare_set.c:23

A2 : 0x3f810500 A3 : 0x0000abab A4 : 0x00060023 A5 : 0x00060021
A6 : 0x0000cdcd A7 : 0xb33fffff A8 : 0x800992f6 A9 : 0x00000001
A10 : 0xb33fffff A11 : 0xb33fffff A12 : 0x3ffbe980 A13 : 0x3ffda140
A14 : 0x3ffc0230 A15 : 0x000927c0 SAR : 0x00000000 EXCCAUSE: 0x00000000
EXCVADDR: 0x00000000 LBEG : 0x40091432 LEND : 0x4009143d LCOUNT : 0x00000000
0x40091432: memset at /builds/idf/crosstool-NG/.build/HOST-x86_64-w64-mingw32/xtensa-esp32-elf/src/newlib/newlib/libc/machine/xtensa/memset.S:150

0x4009143d: memset at /builds/idf/crosstool-NG/.build/HOST-x86_64-w64-mingw32/xtensa-esp32-elf/src/newlib/newlib/libc/machine/xtensa/memset.S:160

Backtrace:0x400d5767:0x3ffbe980 0x400951c8:0x3ffbe9b0 0x4008246a:0x3ffbe9d0 0x4008470d:0x3ffbea30 0x40099a08:0x3ffda090 0x40099b9f:0x3ffda0c0 0x4009eae5:0x3ffda0e0 0x4009f31f:0x3ffda120 0x4009f34d:0x3ffda140 0x4009f1c9:0x3ffda170 0x4008cace:0x3ffda190 0x401425ef:0x3ffda1e0 0x400e06b5:0x3ffda200 0x400e0702:0x3ffda220
0x400d5767: soc_get_available_memory_regions at C:/Users/xxxxxxx/Desktop/esp-idf/components/soc/memory_layout_utils.c:175 (discriminator 3)

0x400951c8: xRingbufferSendFromISR at C:/Users/xxxxxxx/Desktop/esp-idf/components/esp_ringbuf/ringbuf.c:1073

0x4008246a: uart_rx_intr_handler_default at C:/Users/xxxxxxx/Desktop/esp-idf/components/driver/uart.c:893

0x4008470d: _xt_lowint1 at C:/Users/xxxxxxx/Desktop/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1105

0x40099a08: spi_flash_ll_set_command at C:/Users/xxxxxxx/Desktop/esp-idf/components/hal/esp32/include/hal/spi_flash_ll.h:332
(inlined by) spi_flash_hal_configure_host_io_mode at C:/Users/xxxxxxx/Desktop/esp-idf/components/hal/spi_flash_hal_common.inc:133

0x40099b9f: spi_flash_hal_common_command at C:/Users/xxxxxxx/Desktop/esp-idf/components/hal/spi_flash_hal_common.inc:163

0x4009eae5: memspi_host_read_status_hs at C:/Users/xxxxxxx/Desktop/esp-idf/components/spi_flash/memspi_host_driver.c:123

0x4009f31f: spi_flash_chip_generic_read_reg at C:/Users/xxxxxxx/Desktop/esp-idf/components/spi_flash/spi_flash_chip_generic.c:306

0x4009f34d: spi_flash_chip_generic_wait_idle at C:/Users/xxxxxxx/Desktop/esp-idf/components/spi_flash/spi_flash_chip_generic.c:356

0x4009f1c9: spi_flash_chip_generic_erase_sector at C:/Users/xxxxxxx/Desktop/esp-idf/components/spi_flash/spi_flash_chip_generic.c:151

0x4008cace: esp_flash_erase_region at C:/Users/xxxxxxx/Desktop/esp-idf/components/spi_flash/esp_flash_api.c:471

0x401425ef: esp_partition_erase_range at C:/Users/xxxxxxx/Desktop/esp-idf/components/spi_flash/partition.c:522
Attachments
sdconfig.txt
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ESP_Sprite
Posts: 8921
Joined: Thu Nov 26, 2015 4:08 am

Re: IllegalInstruction when UART ISR triggers during SPI FLASH erase/write

Postby ESP_Sprite » Mon Sep 27, 2021 1:36 am

Are you using psram? It might be that somehow your ringbuffer is (partially) allocated there; at least, that's what the backtrace looks like. (Note that psram also 'goes away' when a the cache is disabled when you e.g. write to flash.)

EDIT: Never mind, your sdkconfig says it is. How do you allocate your ringbuffer?


sphudson
Posts: 3
Joined: Fri Sep 24, 2021 4:17 pm

Re: IllegalInstruction when UART ISR triggers during SPI FLASH erase/write

Postby sphudson » Tue Sep 28, 2021 4:51 pm

I have been running v4.3.1, which is the most recent stable release. However, both v4.4-dev and the master IDF branch both have fixes in driver/uart.c to support execution from IRAM. I ran with the master branch and it fixes the issue. The code changes in uart.c are to allow the driver to allocate memory from IRAM rather than SPIRAM.

sphudson
Posts: 3
Joined: Fri Sep 24, 2021 4:17 pm

Re: IllegalInstruction when UART ISR triggers during SPI FLASH erase/write

Postby sphudson » Wed Sep 29, 2021 6:13 pm

Thank you both for your assistance with this. The issue has been resolved by using 4.4-dev or the master branch. I'm sure this will eventually be setup in the next release. Thx again.

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