CPU reduced frequency leads to freeRTOS timing issues

veryDigJJ
Posts: 5
Joined: Fri Sep 25, 2020 12:54 pm

CPU reduced frequency leads to freeRTOS timing issues

Postby veryDigJJ » Mon Nov 29, 2021 9:48 am

Hi,
I am experimenting with a cpu clock frequency reduction on ESP32 mcu. I have a clock frequency of 240 MHz in normal operation mode and switch down to 10 MHz in reduced power consumption mode. However, after reducing the frequency, I can see that the ported freeRTOS timing of functions is reduced - e.g. vTaskDelay(1 / PortTICK_RATE_MS) - delays a task for 1 ms with 240 MHz, but with reduced frequency to 10 MHz, the task is delayed for 24 ms. It seems, the frequency is reduced, but the "system tick" is not altered, accordingly. After looking through ESP_IDF code, I have found an _xt_tick_divisor extern variable, but altering it manually does not seem to give the desired result. Could anyone provide information, on how would it be possible to resolve the freeRTOS timing issue after the frequency reduction?

I am using esp_pm_configure() function of ESP-IDF v4.3.1 to reduce the cpu frequency. And I am aware, that APB frequency is reduced, as well. https://docs.espressif.com/projects/esp ... gurationPv
  1. //just a sketch
  2. #include "esp_err.h"
  3. #include "esp_pm.h"
  4. #include "esp32/clk.h"
  5. #include "freertos/xtensa_timer.h"
  6.  
  7. #define TEN_IN_SIXTH                          (1000000)
  8. #define DEEP_SLEEP_CPU_SPEED         (10 * TEN_IN_SIXTH)
  9. #define NORMAL_CPU_SPEED             (240 * TEN_IN_SIXTH)
  10.  
  11. //frequency reduction function
  12. uint8_t set_CPU_speed(uint32_t speed) {
  13.     uint8_t err = ESP_OK;
  14.     const int low_freq = DEEP_SLEEP_CPU_SPEED / TEN_IN_SIXTH;
  15.     const int hi_freq = NORMAL_CPU_SPEED / TEN_IN_SIXTH;
  16.    
  17.     switch (speed) {
  18.         case DEEP_SLEEP_CPU_SPEED:
  19.             esp_pm_configuration.min_freq_mhz = low_freq;
  20.             esp_pm_configuration.max_freq_mhz = low_freq;
  21.             err = esp_pm_configure(&esp_pm_configuration);
  22.             if (err == ESP_OK) {
  23.                 _xt_tick_divisor = DEEP_SLEEP_CPU_SPEED / XT_TICK_PER_SEC;
  24.             }
  25.             break;
  26.         case NORMAL_CPU_SPEED:
  27.             esp_pm_configuration.min_freq_mhz = hi_freq;
  28.             esp_pm_configuration.max_freq_mhz = hi_freq;
  29.             err = esp_pm_configure(&esp_pm_configuration);
  30.             if (err == ESP_OK) {
  31.                 _xt_tick_divisor = NORMAL_CPU_SPEED / XT_TICK_PER_SEC;
  32.             }
  33.             break;
  34.         default:
  35.             err = 0xFF;
  36.             break;
  37.     }
  38.     return err;
  39. }
As well, I have configured:
  1. CONFIG_FREERTOS_HZ=1000

veryDigJJ
Posts: 5
Joined: Fri Sep 25, 2020 12:54 pm

Re: CPU reduced frequency leads to freeRTOS timing issues

Postby veryDigJJ » Tue Nov 30, 2021 7:39 am

After all, adjusting the value of _xt_tick_divisor *does* solve the freeRTOS timing. Appearantly, the timing of my system suffers because of flash memory read/write over the SPI.

Who is online

Users browsing this forum: ESP_Roland, expupil and 121 guests