Dual Core halt

weslleymfd
Posts: 3
Joined: Thu Jan 13, 2022 1:44 pm

Dual Core halt

Postby weslleymfd » Thu Jan 13, 2022 1:57 pm

Hello,

I'm working on a project that utilize the ESP-WROVER-E module.

In this project, APP_CPU_NUM is used to acquire ADC data trough SPI and processes it. All functions that process this data are being called from the task that was initialized in APP_CPU_NUM.

In the PRO_CPU_NUM we have a routine that stores this data every X amount of minutes.

The problem that I encountered is: when the task that stores the data calls the file operations (I'm using FATFS partitions) on the PRO_CPU_NUM core, the APP_CPU_NUM halts for the duration of the writing file operations.

Aren't this 2 tasks/cores supposed to be totally independent. Am I missing something?

Best regards,
Weslley

ESP_Sprite
Posts: 8922
Joined: Thu Nov 26, 2015 4:08 am

Re: Dual Core halt

Postby ESP_Sprite » Fri Jan 14, 2022 3:27 am

They are, but they share a common path to the flash. The thing is that ESP32 programs, by default, execute from flash (but via a cache to make execution a lot faster). If you write to flash, that flash is not available to execute from, and the writing code will stop any tasks and interrupts that are not marked as being fully in IRAM.

If you could tell us a bit more about what your app CPU task does and the nature of the writes, perhaps we can help to find a solution that works without interruption.

weslleymfd
Posts: 3
Joined: Thu Jan 13, 2022 1:44 pm

Re: Dual Core halt

Postby weslleymfd » Fri Jan 14, 2022 12:29 pm

Hi ESP_Sprite,

Thanks for the reply.

The code on the APP_CPU_NUM reads the ADC data and converts it to some electrical quantities (voltage, current, power ...). This measurement occurs in windows of precisely 350ms.

The code on the PRO_CPU_NUM takes this data, and data from all other analog/digital inputs, process it, stores it in flash when necessary and generates multiple alarms that are later sent via MQTT to the server.

The idea we had to segregate the main analog measurements from all other "less important" inputs, was to loss as few data as possible from the main ADC, running it in a continuous loop.

Now, if reading/writing to flash from the APP_CPU_NUM halts the tasks on the PRO_CPU_NUM core, I guess we only have the option to synchronize this write/read operations (with semaphores for example) to never occur when we are taking measurements with the ADC.

Do you have any other ideas?

Thanks in advance.
Weslley

ESP_Sprite
Posts: 8922
Joined: Thu Nov 26, 2015 4:08 am

Re: Dual Core halt

Postby ESP_Sprite » Sun Jan 16, 2022 1:51 am

Gotcha. I think your idea of using a semaphore to synchronize the writes is a nice one. Additionally, I'd make sure never to write more than 4K in one go (as in: delay a few ticks between 4K writes): the underlying FS layer may need to erase the flash on a write, and the larger the erase, the longer it takes. Note that for some (old?) flash chips, you may still miss a reading or two, as theoretically 4K flash erase (4k is the smallest block) can still take longer than 350ms.

The alternative would be to do the ADC reading in an IRAM interrupt (which will keep running when flash is written), but you may not be able to use the ADC driver API there as I don't think that is fully in IRAM. If all you do is grab a value from the ADC, that may be a feasible option, though.

weslleymfd
Posts: 3
Joined: Thu Jan 13, 2022 1:44 pm

Re: Dual Core halt

Postby weslleymfd » Mon Jan 17, 2022 11:13 am

Hello, ESP_Sprite.

I will definitely evaluate all possibilities you suggested.

Thanks for the help.

This topic can now be closed.

Best regards,
Weslley

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