ESP32-C3 RDCYCLE

[fabianpedd]

How do I access the RISC-V performance counters, namely CYCLE, TIME, and INSTRET on the ESP32-C3 (see Chapter 10 RISC-V spec)? I am running the ESP-IDF.

Running

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__asm__ volatile("rdcycle %0" : "=r"(cycles));

or

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__asm__ volatile("csrrs %0, cycle, x0" : "=r"(cycles));

results in illegal instruction exceptions. However, they work on other platforms.

Thanks in advance

EDIT: It seems like Espressif decided to implement their own perf counter instead of using the one(s) specified by the RISC-V standard. If you are looking for a register that returns the cycle count, just like

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CYCLE

,

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MPCCR

is probably what you are looking for. It is located at

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0x7E2

in the CSRs address space and documented under "Performance Counter CSRs (Custom)" in the technical reference manual. There seems to be a C function (not documented in the ESP-IDF for whatever reason) that can be used to read it conveniently from C applications:

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esp_cpu_ccount_t esp_cpu_get_ccount(void)

(see here https://github.com/espressif/esp-idf/bl ... _cpu.h#L61).

[fabianpedd]

Does anyone have any idea?