ESP32 Forum

I'm trying to get an accurate timer or counter for my project. Now I'm using ccount and ccompare as the timer, but find it has a periodical variation (0.75Hz), which should be caused by the voltage variation due to WiFi power consumption changing.

So I'm thinking if the timer group can use the external oscillator as the clock source, which should be more accurate than PLL clock. I checked the technical reference manual, according to the section on the Clock System and Peripheral Clock (as attached below), the clock source of the timer group can only be APB_CLK, which comes from CPU_CLK. CPU_CLK could be derived from the external oscillator, but with the external oscillator, the CPU frequency can only be < 40 MHz, which is too slow.

So it seems if I run ESP32 at 240 MHz, the clock source of the timer group has to be the internal PLL clock; If I want to use the external oscillator, the CPU frequency has to be < 40MHz. Is my understanding correct? If that's true, it's really a bad news to me. Is there any workaround to have both 240MHz CPU frequency and timer with the external oscillator? Or is it theoretically impossible since the 480M PLL clock can not synchronize with the 40M oscillator clock?

One of the clock sources of I2S is Audio PLL, which seems to be sourced from the crystal oscillator and ranges between 350MHz and 500MHz. Is it possible to use APLL as the clock source of some timer and trigger interrupt?

Does anyone have any information about the question?
Is it possible to have the timer clocked by 40M crystal oscillator via XTL_CLK or APLL_CLK while have 240M CPU frequency?

When the PLL is locked (which would generally be 'always' if your software runs) the PLL is exactly as accurate as your crystal. It needs to be as WiFi baseband also uses it and WiFi needs an accurate clock.

Thank you Sprite, I'm glad to hear that. I may be asking stupid questions, are you saying the external 40M crystal oscillator is the input of the PLL_CLK circuit? PLL is a phasor lock loop, it will output the same frequency with its input. But if the input is a R-C oscillator, the output of PLL may also not be that accurate. I didn't find any information about the input signal of the PLL_CLK of ESP32.

In our project we find a 0.75 Hz periodical time variation, the variation magnitude is around 37 ns. The variation pattern and period is the same with ESP32 power consumption variation caused by Wifi, as shown below. The 37 ns time changing contributes the majority of the error, so I'm trying to find some solution to reduce this periodical error. We thought the voltage variation (0.2mV) may be the reason, but it didn't help when we reduced the voltage variation to 0.3mV at the ESP32 VDDA or VDD3P3 pin.
It's fine if there is no solution for that, the accuracy is good enough for now. But it will always be good to make it as accurate as possible.

Current of ESP32 module Time Error in our project.

Yes, the 40MHz crystal is normally used as the input to the PLL. I think we specify 'less than 10ppm' deviation on the clock signal, so 0.75Hz would be in spec there.

I see! Thank you very much.