ESP32 Forum

Yes I will get you some number on the bck jitter - and the APLL buggy frequency calculation is now were to be found.

/j

Hi
I have stable stereo mp3 audio through the device - I need to do some small code clean up and expect to commit by the end of the week. Very nice work from all involved.

Single issue outstanding is the clock jitter due to APLL not correct setup/running.

I measured the i2s_bck clock jitter for 128 kbps 44.1 kHz mp3 stream - estimate that to add 20 dB to the noise floor - still not bad but...



When that is fixed we have a very nice and potential setup ....

Regards Jørgen

Hi Buddy
I have commited my 2ch update to you repo - please let me know if i succeeded - I am a svn guy
/j

I don't see anything. If you're coming from SVN, working with git can be confusing at first - I've been there too.

The way this works is:

• you fork my repo, you then have an independent copy of the repository on your github account
• do "git clone" to download the fork you just made to your local machine
• you can now make your changes directly on the master branch (or preferably on a separate feature branch)
• commit your changes using "git commit", note that this will only affect your local repo on your local machine
• to sync your local repo to your github repo, make sure to "git push" your changes
• now you can create a "pull request", asking me to merge back the changes you made in your fork

Mentally its a very different model from SVN, and unfortunately Git is not that user friendly. But once you get it, you will never want to go back to SVN.

If you have trouble I'm happy to help.

Hi Buddy
O yes - need more coffee - i did commit - as I use to on SVN but i see there is more to it then that.
I will try to follow you description tonight and have added git to my bucket list.
Thanks /j

Hi Sprite

Do you have any numbers to go with that jitter? Fyi, we have a separate audio PLL in the ESP32, but unfortunately the details of that aren't public yet (as in: I'd love to tell you here, but I don't have any internal docs on it and our HW engineers are on holiday). Maybe enabling that can help; I'll ask around after Chinese new year.

Did you get at change to talk to the hardware team regarding APLL clock jitter.
Merus Audio EVK and snowball demo board on its way to Shanghai

/j

Fancy! Wrt APLL jitter: The driver actually does not use the APLL at the moment; it divides down an internal 160MHz signal using a fractional divider. This causes the jitter you see. I'm asking around if we have example code to configure the APLL somewhere; although there's a bug in it for the first generation of silicon (it ignores some dividers) it may be enough to get a more stable BCLK signal.

@ESP_Sprite: it seems supply of ESP32 modules has dried up, is production currently halted due to the silicon bugs? If yes, do you have a rough idea when they will be available again?

Could be, yes. We should get the new silicon this week, I guess general availability won't be too far off from there.

Hi BuddyCasino

Let me know if you are in urgent need. I got 10 from the first batch and can share a few. We cant have you not working on the esp32 devices

/j