ESP32 Webradio

[WiFive]

Might help with apll

https://esp32.com/viewtopic.php?f=2&t=8 ... t=10#p5869

[rudi ;-)]

Its going to be on Github as soon as I got it to work.

we did it in the meantime

[BuddyCasino]

Thats ok. I won't fret.

[Jakobsen]

Hi WiFive

Thanks for the hint - No no sign of an APLL enabled by that call. Parameter change did do something but not any thing deterministic - and still a lot of jitter on BCK

/j

[rudi ;-)]

Hi WiFive

Thanks for the hint - No no sign of an APLL enabled by that call. Parameter change did do something but not any thing deterministic - and still a lot of jitter on BCK

/j

perhabs you must change the register too:

clk_reg_1.jpg (73.02 KiB) Viewed 2784 times

clk_reg_2.jpg (89.37 KiB) Viewed 2784 times

clk_reg_3.jpg (41.48 KiB) Viewed 2784 times

cut from lib

rtc_clk.o rtc_xtal_32k_ena
rtc_clk.o rtc_8m_ena
rtc_clk.o rtc_plla_ena
rtc_clk.o rtc_set_slow_freq
rtc_clk.o rtc_set_fast_freq
rtc_clk.o rtc_bbpll_md
rtc_clk.o rtc_init_xtal_freq
rtc_clk.o rtc_get_xtal
rtc_clk.o rtc_apb_freq_up
rtc_clk.o rtc_uart_div_modify
rtc_clk.o rtc_uart_tx_wait_idle
rtc_clk.o rtc_set_cpu_freq
rtc_clk.o rtc_init_clk
rtc_clk.o rtc_init_clk_lite

perhabs it helps you

[rudi ;-)]

my setup test was from 2.5 MHz do 154 MHz
each higher pos was more clear as the preview

example 2.5 MHz ( Jitter )

Code: Select all

rtc_plla_ena(1, 0, 255, 0, 0); // 2.5MHz

2.50MHz.jpg (108.62 KiB) Viewed 2783 times

info for the choice of src of clock and register are in the technical docu too

clk_reg_a.jpg (83.85 KiB) Viewed 2783 times

hope this helps.

[WiFive]

Maybe https://github.com/espressif/esp-idf/bl ... i2s.c#L161

[rudi ;-)]

yeap, WiFive is right.

316 kHz

316kHz.jpg (104.44 KiB) Viewed 2780 times

you must play with the clk register itself too
and we must use the right src
there are many parameters possible, better we wait for the docu
we can stretch time too ( ? ! )
we can polarisation too ( ? ! )
we can invert too ( ? ! )
we can do more ( ? ! )

i think "my" setup was the best for 10MHz ..160 MHz
if we want smaller we need a fine tuning with other src by choice the right register.

best wishes
rudi

[rudi ;-)]

played with the stretching and polarisation
same 316KHz
but :

5_10

316kHz_5_10.jpg (104.88 KiB) Viewed 2779 times

6_10

316kHz_6_10.jpg (109.21 KiB) Viewed 2778 times

8_10

316kHz_8_10.jpg (109.86 KiB) Viewed 2776 times

with more playtime the jitter can be compensated
and there are differences with
-> DevKitC V1
-> DevKitC V2
-> DemoBoard V2
-> Wrover V1
-> Wrover V2
-> ...

i mean, the jitter make sig time delayed waved, perhabs a caps to much in the line?
.. i do not know .. i am

hardware hobbiest

[rudi ;-)]

O yes - need more coffee - i did commit - as I use to on SVN but i see there is more to it then that.
I will try to follow you description tonight and have added git to my bucket list.

Any progress?

Its going to be on Github as soon as I got it to work.

Any progress
Where are you stuck

best wishes
rudi