I did change the plla_ena in the i2s code as well. It is the jitter that we need to reduce. For audio codec and i2s interface with out faster MCKL in the setup, the jitter on BCK crank up the noise floor in the audio band.
We need more insight to the esp32 clock system to get the apll going - the audio quality is good for now - just no CD quality yet.
Do not down play you hobby approach to this stuff - you got you hand more dirty then most professional has the skills to do.
I am stocked by work and lag of focus - I am working some dsp stuff that also will be needed to do a top notch platform.
Code: Select all
clkmInteger = clkmdiv;
clkmDecimals = (clkmdiv - clkmInteger) / denom;
float mclk = clkmInteger + denom * clkmDecimals;
bck = factor/(bits * channel);
// rtc_plla_ena(1, 0, 0,1 , 0);
I2S[i2s_num]->clkm_conf.clka_en = 1; // jkj was 0
I2S[i2s_num]->clkm_conf.clkm_div_a = 63;
I2S[i2s_num]->clkm_conf.clkm_div_b = clkmDecimals;
Analog Digital IC designer / DevOps @ Merus Audio, Copenhagen, Denmark.
We do novel and best in class Audio amplifiers for consumer products.
Programmed assembler for C-64 back in 1980's, learned some electronics - hacking since then