I mean s2 with s1, s4 with s3...
I believe ESP_igrr knows why.
Hi EUA,Since we are reading (RX) from I2S, ESP32 expect external clock not use internal derived one.
I pass this requirement via feeding a pin via generated external clock signal and routing to I2S clk pin. But after 20Mhz, it doesn't work proper.
Than I will use extra ram buffer to expand sampling on it.
I am little sad about sampling speed which is limited to 20Msps.
I found that If I use QSPI interface, I can sample up to 80Msps 4bit but I am not sure if it supports such a long RX reception.
But found that Arduino-esp32 don't support QSPI DMA, yet.
Otherwise I plan to use Dual QSPI with DMA to archive 80Msps 8Bit device implementation.
If I found such a some sample, will try to implement it also.
How can I apply this patch? Where?You can use this patch https://sigrok.org/bugzilla/show_bug.cgi?id=1025 for PulseView/Sigrok work proper.
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// Configure Bit Clock configuration - ESP32 Tech Reference page 308 and 337 // fi2s = fpll / (N + b/a) = 160 MHz / (4 +(0/1) = 40 MHz (using PLL_D2 clock) I2S0.clkm_conf.clkm_div_num = 4; // I2S clock divider’s integral value >= 2 I2S0.clkm_conf.clkm_div_b = 0; // Fractional clock divider’s numerator value I2S0.clkm_conf.clkm_div_a = 1; // Fractional clock divider’s denominator value I2S0.clkm_conf.clk_en = 1; // I2S clock enable I2S0.clkm_conf.clka_en = 0; // Set this bit to enable clk_apll
Okay. Than you will clearly understand why.
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ets Jun 8 2016 00:22:57 rst:0x1 (POWERON_RESET),boot:0x16 (SPI_FAST_FLASH_BOOT) flash read err, 1000 ets_main.c 371 ets Jun 8 2016 00:22:57 ...
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