ESP32 debug Eclipse+OpenOCD+JLink issue

newsettler_AI
Posts: 121
Joined: Wed Apr 05, 2017 12:49 pm

ESP32 debug Eclipse+OpenOCD+JLink issue

Postby newsettler_AI » Thu Jun 22, 2017 11:49 am

Hi,

I have issue with hardware debugging of ESP32 module (I have CoreBoard V2). I want to debug esp32 through J-Link


My Eclipse is configured properly (I can compile&flash throung serial from eclipse).

When I'm trying to run debug, I got next error:

Code: Select all

Open On-Chip Debugger 0.10.0-dev-g90071eb (2017-02-12-00:28)
Licensed under GNU GPL v2
For bug reports, read
 http://openocd.org/doc/doxygen/bugs.html
adapter speed: 2000 kHz
force hard breakpoints
Started by GNU ARM Eclipse
Info : J-Link ARM V8 compiled Nov 28 2014 13:44:46
Info : Hardware version: 8.00
Info : VTarget = 3.293 V
Info : clock speed 2000 kHz
Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : esp32.cpu0: Debug controller was reset (pwrstat=0x5F, after clear 0x0F).
Info : esp32.cpu0: Core was reset (pwrstat=0x5F, after clear 0x0F).
Info : accepting 'gdb' connection on tcp/3333
Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : esp32.cpu0: Core was reset (pwrstat=0x1F, after clear 0x0F).
Info : esp32.cpu0: Target halted, pc=0x40000400
esp32.cpu0: target state: halted
Error: timed out while waiting for target halted
TARGET: esp32.cpu1 - Not halted
in procedure 'reset' 
in procedure 'ocd_bouncer'


Info : Halt timed out, wake up GDB.
Error: timed out while waiting for target halted

Info : Auto-detected RTOS: FreeRTOS
Error: esp32.cpu0: xtensa_write_memory (line 1024): DSR (8020CC13) indicates DIR instruction generated an exception!
Warn : esp32.cpu0: Failed writing 4096 bytes at address 0x3F400010
Error: esp32.cpu0: xtensa_write_memory (line 1024): DSR (8020CC13) indicates DIR instruction generated an exception!
Warn : esp32.cpu0: Failed writing 4096 bytes at address 0x3F401010
Info : dropped 'gdb' connection
Please advice!

ESP_Sprite
Posts: 8926
Joined: Thu Nov 26, 2015 4:08 am

Re: ESP32 debug Eclipse+OpenOCD+JLink issue

Postby ESP_Sprite » Thu Jun 22, 2017 1:00 pm

What program are you trying to debug? Do you happen to use (one or more of) the GPIOs used for JTAG (GPIO12-15) for other purposes in your program?

ESP_igrr
Posts: 2067
Joined: Tue Dec 01, 2015 8:37 am

Re: ESP32 debug Eclipse+OpenOCD+JLink issue

Postby ESP_igrr » Thu Jun 22, 2017 4:03 pm

Code: Select all

Warn : esp32.cpu0: Failed writing 4096 bytes at address 0x3F400010
Based on this part of the log, I would say that Eclipse is not configured properly, as it is trying to instruct GDB to load the elf file into the ESP32. This will not work because the OpenOCD version currently available is not able to program flash memory of the ESP32.
You likely need to disable loading of the program into target's memory.

Also be advised that the current master branch of OpenOCD only works with an IDE if it is configured for single core debugging.

newsettler_AI
Posts: 121
Joined: Wed Apr 05, 2017 12:49 pm

Re: ESP32 debug Eclipse+OpenOCD+JLink issue

Postby newsettler_AI » Tue Jun 27, 2017 3:24 pm

I have one more issue - my Jlinks is not found.
I'm working on windows 7.

Here is output from msys32:

Code: Select all

admin@workpc MSYS ~/openocd-esp32
$ openocd -f esp32.cfg
Open On-Chip Debugger 0.10.0-dev-gebfc3bad (2017-06-27-15:50)
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
Error: The specified debug interface was not found (jlink)
The following debug interfaces are available:

This is my esp32.cfg:

Code: Select all

#
# Example configuration file to hook up an ESP32 module or board to a JTAG 
# adapter. Please modify this file to your local setup.
#
#


# Include the configuration for the JTAG adapter. We use the Tian TUMPA here.
# If you have a different interface, please edit this to include the 
# configuration file of yours.
source [find interface/jlink.cfg]

# The ESP32 only supports JTAG.
transport select jtag

# The speed of the JTAG interface, in KHz. If you get DSR/DIR errors (and they
# do not relate to OpenOCD trying to read from a memory range without physical
# memory being present there), you can try lowering this.
adapter_khz 2000

# With no variables set, openocd will configure JTAG for the two cores of the ESP32 and
# will do automatic RTOS detection. This can be be adjusted by uncommenting any of the
# following lines:

# Only configure the PRO CPU
#set ESP32_ONLYCPU 1
# Only configure the APP CPU
#set ESP32_ONLYCPU 2
# Disable RTOS support
#set ESP32_RTOS none
# Force RTOS to be FreeRTOS
#set ESP32_RTOS FreeRTOS

#Source the ESP32 configuration file
source [find target/esp32.cfg]


# The TDI pin of ESP32 is also a bootstrap pin that selects the voltage the SPI flash
# chip runs at. When a hard reset happens (e.g. because someone switches the board off
# and on) the ESP32 will use the current TDI value as the bootstrap value because the
# JTAG adapter overrides the pull-up or pull-down resistor that is supposed to do the
# bootstrapping. These lines basically set the idle value of the TDO line to a 
# specified value, therefore reducing the chance of a bad bootup due to a bad flash
# voltage greatly.

# Enable this for 1.8V SPI flash
#esp108 flashbootstrap 1.8
# Enable this for 3.3V SPI flash
esp108 flashbootstrap 3.3
And this is jlink.cfg:

Code: Select all

#
# SEGGER J-Link
#
# http://www.segger.com/jlink.html
#

interface jlink

# The serial number can be used to select a specific device in case more than
# one is connected to the host.
#
# Example: Select J-Link with serial number 123456789
#
# jlink serial 123456789
jlink serial 304439649

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