What would you like to see in The Next Chip?

rin67630
Posts: 64
Joined: Sun Mar 11, 2018 5:13 pm

Re: What would you like to see in The Next Chip?

Postby rin67630 » Tue Mar 20, 2018 10:34 pm

ESP_Sprite wrote:How do you mean, wake from deep sleep without hardware modifications? Also, what use case would you have to compile sepate things for both cores?

...wake from deep sleep without having to tie a pin to RST.
Compile one core to gather data and the other one to form/transmit data.

ESP_Sprite
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Joined: Thu Nov 26, 2015 4:08 am

Re: What would you like to see in The Next Chip?

Postby ESP_Sprite » Wed Mar 21, 2018 1:38 am

On the ESP32, there's no need to tie RST to GPIO16; that is an ESP8266 thing. And with the current SDK you can already happily start a thread on one core to collect data and one on the other core to send it. Are you sure you have worked with the ESP32 before, and are not confusing it with the ESP8266?

-31253-
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Joined: Fri Mar 23, 2018 7:44 am

Re: What would you like to see in The Next Chip?

Postby -31253- » Fri Mar 23, 2018 8:28 am

CAN 2.0 module , more UART module, maybe some functional safety module and software, compliance with IEC61508\IEC60730 standard,,etc

barometre
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Re: What would you like to see in The Next Chip?

Postby barometre » Thu Mar 29, 2018 10:37 am

Hi,

After using ESP32 till this time, my revised suggestions would be like this:

-5ghz support
-USB 2.0 slave/host options.
-Some kind of lcd interface, preferably lvds
-Internal video decoder/encoder (doesnt have to 1080p or something low res is okay)
-TDM audio
-Small DSP for audio
-Preferably bluetooth chip can have fm receiver too but not very important.
-Low res camera interface

With these futures it will have wide use areas. Like usb dongles, media players etc... If it would have video decoder and video output option it can be even used as cheap android auto receiver.

rin67630
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Re: What would you like to see in The Next Chip?

Postby rin67630 » Sun Apr 15, 2018 10:58 am

On the next package like WROOM I'd expect an integrated 32.768KHz/10ppm Xtal for a decent sleep timing.

davydnorris
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Joined: Thu Sep 15, 2016 8:11 am

Re: What would you like to see in The Next Chip?

Postby davydnorris » Tue Apr 17, 2018 3:58 am

Wi-Fi RTT: We actually have a fair bit of the hardware needed for something like this already; we just haven't had any requests from big customers to write the added driver support for it (at least, that's what I understand); also, I'm not sure if hardware support actually has been tested in any way; for all we know it may be broken. Don't be surprised if something like this pops up in esp-idf in an upcoming version, however.


Apart from the common 5GHz wifi request, this would be very interesting to me. I am working on two areas that would benefit from this:
- large scale mesh networks that work with deep sleep
- real time protocol (RTP) for Audio over IP applications using AES67 or RAVENNA

In each case, having a high precision RTC and the ability to precisely synch each device's RTC over the network is essential

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ninjaneer
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Re: What would you like to see in The Next Chip?

Postby ninjaneer » Thu Apr 19, 2018 6:56 pm

I was going through MS's new security white paper on what they've identified for their devices, Seven Properties of Highly Secure Devices, and of course the hardware based root-of-trust one is the piece that stands out. It would be nice to have a hardware-implemented, cryptographically-backed way to identify and certify each chip.

The rest looks nice, but it's something that most serious scada engineers can implement on an as-needed, roll-your-own-for-obscurity basis.

markwj
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Re: What would you like to see in The Next Chip?

Postby markwj » Thu Apr 19, 2018 11:58 pm

No more dual-use strapping pins, please. The GPIO2 and GPIO12 vs SD CARD has been a nightmare for us. Overall, messing around with SD CARD issues probably set our project back about 6 months.
Last edited by markwj on Mon Apr 30, 2018 5:08 am, edited 1 time in total.

daslolo
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Re: What would you like to see in The Next Chip?

Postby daslolo » Sun Apr 29, 2018 3:16 am

LVDS would expand our display options and would require a 2D accelerator https://www.reddit.com/r/esp32/comments ... the_esp32/

If it's possible, a section of the chip is an FPGA then we'd have possibly super high speed IO, but FPGA would have to be configurable by C code alone so in the Arduino layer we could make cool things whilst remaining lazy :D

burtrum
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Re: What would you like to see in The Next Chip?

Postby burtrum » Mon Apr 30, 2018 1:59 pm

1. Mechanical Switch Debounce in HW.
2. Rotary Encoder Switch Decoder.

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