Re: ESP32 Free Heap
Postby Sprite_tm » Tue Dec 15, 2015 5:21 pm
Sure. I have no docs I can release of that, but very quickly: The ESP31 has three regions of RAM: an IRAM for the first cpu at 0x40040000 (which is 128K), an IRAM for the second CPU at 0x3ffa8000 (64K) and a shared RAM at 0x3FFD8000 (192K). The IRAMs actually are 32K bigger than that, but if SPI cache is enabled on the corresponding CPU, that region is not usable. (The addresses I mention are the addresses I know of by which the 1st CPU can addres the memory; they're slightly different for the 2nd CPU and they're also not the only address ranges the RAM is mapped to.)
The SDK puts most of the program code in the IRAM of the first CPU, and the heap+stack in the shared RAM. This means there is still some memory that isn't used by default on the end of the IRAM segment of the 1st CPU. Also, with the 2nd CPU not used as it is in the current SDK, there is 92K of RAM in its IRAM region that is usable but not used by default.
Re: ESP32 Free Heap
Postby rojer9 » Wed Dec 16, 2015 5:41 am
thanks for the explanation of the memory map Jeroen, it makes sense, except for this:
in your reply you mention that the region at 0x3FFD8000 is the shared 192K segment.
but there's only 144K between 0x3FFD8000 and 0x40000000 which is where ROM starts.
does it mean that there is 48K before that that can be used?
Not sure about the above. If the shared RAM is 192K (0x30000) and starts at 0x3FFD8000 then it would end at 0x40008000.
However as Rojer9 points out the on-chip ROM seems to start at 0x40000000 if the exception vector addresses in the SDK are correct.
If the shared ROM starts at 0x3FFD8000 and finishes at 0x3FFFFFFF then it's size would be 0x28000 (160K).
However according to eagle.pro.v7.ld in the SDK it's length is 0x24000 (144KB)
dram0_0_seg : org = 0x3FFD8000, len = 0x24000
So is the shared ROM 144K, 160K, or 192K or are some of the addresses wrong?
Also if the IRAM for the 2nd CPU was 64K + 32K SPI Cache that adds up to 96K instead of the 92K given. Is there a mistake here or am I missing something?
So according to what you have said and eagle.pro.v7.ld this is what I think is the resultant RAM memory map according to the 1st CPU.
IRAM 1st CPU = 128K + 32K SPI Cache = 160K @ 0x40040000
IRAM 2nd CPU = 64K + 32K SPI Cache = 96K @ 0x3FFA8000
DRAM Shared = 144K @ 0x3FFD8000
Total RAM = 400K
The total RAM neatly agrees with the press releases. Is the above memory map correct for ESP31?
Need to know because the amount of DRAM is very important for the application I am working on (Ideally I require a 100K buffer for an incoming stream but I can settle for less).