ESP32 Forum

WiFive wrote: ↑

Mon Mar 25, 2019 6:27 am

Sounds like it is basically "esp32+" or "esp33". I think we can mention small things that are hopefully fixed/upgraded from esp32 since it is not in production yet, there is still time!

- More psram cache address space
- More flash cache address space
- better ulp core (some tiny xtensa thing?, c targetable)
- minimal iomux conflicts
- better i2c peripheral, support clock stretching, slave address mask, monitor/debug mode
- support espnow and ble advertising from rom/ram only (wake stub, no flash load)
- BLE 5 phy features
- better continuity of reserved ram areas

Review the wish list...
- More psram cache address space ✓
- More flash cache address space ✓
- better ulp core ✓
- minimal iomux conflicts ✓ (we'll assume more pins means yes)
- better i2c peripheral, support clock stretching, slave address mask, monitor/debug mode (maybe)
- support espnow and ble advertising from rom/ram only (wake stub, no flash load) ✖
- BLE 5 phy features ✖
- better continuity of reserved ram areas ✓ (probably)

I think the I2C slave implements some kind of clock stretching now, so there's at least half a ✓ more

ESP_Sprite wrote: ↑

Fri May 24, 2019 3:33 am

I think the I2C slave implements some kind of clock stretching now, so there's at least half a ✓ more

Will it be able to load and run programs from PSRAM?

I think psram also has I-port access now, so yes.

ESP_Sprite wrote: ↑

Fri May 24, 2019 6:06 am

I think psram also has I-port access now, so yes.

incredible moment
if that's possible - who should be able to top that setup?
espressifer's digi guys - keep up the very good work !!
the last 5 years we have invested well, I do not regret a minute.
Excellent!

best wishes
rudi

few things are spotted in the wild last hour's..

Engineering Board PIC taken from the ESP32-S2 demo 1 , also here
best wishes
rudi

May I ask - why not 2 cores?

Because cheaper. We're still of the opinion multiple cores is a good idea, just not in this specific chip.

Well, 240MHz is well enough. Although, in this case FreeRTOS could be excluded entirely, and maybe, the chip's resources could be used more efficiently.

However I still think that in more complex cases FreeRTOS or something simillar can still be a good option.

One request for the devs: Please make a WROVER style module from the start. Also - I guess I probably ask too much - but make an IDF config option to be able to configure the chip to be able to correctly run code from PSRAM.

I can strongly predict, that as soon as this is launched, someone will make an OS for the chip, and not long after, someone will port a Linux onto this thing - thanks to the PSRAM instruction running capability, and 128MB PSRAM support!

ESP_Sprite wrote: ↑

Sat May 25, 2019 11:37 am

Because cheaper. We're still of the opinion multiple cores is a good idea, just not in this specific chip.

mhm one core, dual core,
what is with ( pspspspspspsp ) ESP32-S3x
how much cores?
can you wisper a little? ( only little, come on )


not that i did not say it - but have everyone noted that the NEW is not LX6 but it is LX7 ?
2 FLOPS / cycle for the LX6, but 64 FLOPS / cycle for the LX7 ( Info ENG , Info DE )

hosa

espressif's own DSP is comming

exciting year!

best wishes
rudi