Documentation of functions implemented in ROM would be also nice.
Technical reference manual also does not correspond with ESP-IDF (many registers / register bits are missing).
- DPORT_APP_CACHE_CTRL1_REG is missing (it is according to ESP-IDF very important to work around a hardware bug
- how to set pad hold feature of GPIO32 / GPIO33 ?
- how to set RTC function to RTC_GPIO / RTC_I2C ?
- in RTCIO_RTC_GPIO_OUT_REG it is possible to set output value of some pins that are input only, that is kind of misleading
As I would like to implement a custom SDK I believe that there is more I am about to discover
- addresses of RTC registers are in sections 30.4 and 30.5 increased by 1 instead of 4
- setting CPU frequency is not well documented (RTC8M and RTC_CLK need to be calibrated, how to do that? when changing CPU frequency there is needed to set DBIAS voltage - how to set it correctly?)
- SPI flash options in SPI registers are not documented (e. g. SPI_FLASH_READ, SPI_FLASH_WREN in SPI_CMD_REG register)
- as I have read here https://github.com/espressif/esp-idf/issues/1346#issuecomment-368740348 it is very unclear how to correctly setup SPI timing; I am missing info about SPI mode - DMA incompatibility
The most critical si clock configuration section. Have no clue what is ANA_CONFIG_REG (0x6000E044), BBPLL, APLL (it has something to do with some internal I2C bus?)
Where in Figure 6: System Clock fits RTC 8 MHz clock divider https://github.com/espressif/esp-idf/blob/568da37af74dfbbd69392b6d38bfcfff1e5a48fc/components/soc/esp32/rtc_clk.c#L698-L699
Please give us complete scheme with all clock configuration options.