ESP32-S3 LCD and I2S FULL documentation

Baldhead
Posts: 341
Joined: Sun Mar 31, 2019 5:16 am

Re: ESP32-S3 LCD and I2S FULL documentation

Postby Baldhead » Tue Dec 28, 2021 11:49 pm

Baldhead wrote:
Mon Dec 27, 2021 1:34 am
ESP_Sprite wrote:
Fri Dec 24, 2021 1:33 am
Looked it up... the reason you can't put more into the L1FIFO is that it's tiny: only 24 bytes (which I assume is organized in 3 words). I'm not sure why data doesn't get pulled through to l2/l3fifo (especially l2fifo is larger at 128 bytes), perhaps that mechanism only starts when the peripheral starts a transaction.

EDIT: Never mind, I see that push operations only push 8 bit into the FIFO. Hmm, then I can't really explain the l1fifo behaviour you're seeing... will ask to see if the digital team knows more. By the way, it's likely that the bus between l1fifo and l2fifo is larger than 8 bit, so you'd expect the l1fifo to only empty into the l2fifo once the l2fifo collected 32 or maybe even 64 bit. You are sure the fill numbers there do not change even if you put >8 bytes into the l1fifo?
Hi @ESP_Sprite,

My observations (i don't know if they are correct or not):

L1 only transfer to L2 when L1 have 8 bytes.

L1 count unit is byte ( GDMA.channel[channel].out.outfifo_status.outfifo_cnt_l1 = 1 is equal to 1 byte )
L2 count unit is 8 byte ( GDMA.channel[channel].out.outfifo_status.outfifo_cnt_l2 = 1 is equal to 8 bytes )
L3 count uint is byte ( GDMA.channel[channel].out.outfifo_status.outfifo_cnt_l3 = 1 is equal to 1 byte )

Esp32-s3 technical reference manual: Pre-release v0.3, page 108
GDMA_OUTFIFO_CNT_L1_CHn The register stores the byte number of the data in L1 TX FIFO for TX channel 0. (RO)
GDMA_OUTFIFO_CNT_L2_CHn The register stores the byte number of the data in L2 TX FIFO for TX channel 0. (RO)
GDMA_OUTFIFO_CNT_L3_CHn The register stores the byte number of the data in L3 TX FIFO for TX channel 0. (RO)

Esp32-s3 technical reference manual: Pre-release v0.3, page 78
L1FIFO, L2FIFO and L3FIFO have fixed depth: 24, 128, and 16 bytes, respectively.

L1 size = 16 bytes
L2 size = 80 bytes
L3 size = 16 bytes

// gdma_struct.h
GDMA.sram_size[channel].out.out_size = 8; // This register is used to configure the size of L2 Tx FIFO for Tx channel 0.
// 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes.

All multiples of 8: ( relevant or not?! )
0: 16 bytes = 2*8
1: 24 bytes = 3*8
2: 32 bytes = 4*8
3: 40 bytes = 5*8
4: 48 bytes = 6*8
5: 56 bytes = 7*8
6: 64 bytes = 8*8
7: 72 bytes = 9*8
8: 80 bytes = 10*8

Code: Select all

void app_main(void)
{  
    esp_err_t r = hw_lcd_init();
    printf("r = %s\n\n", esp_err_to_name(r));
    
    uint8_t data[32];
    
    data[0] = 0x01;
    data[1] = 0x02;
    data[2] = 0x04;
    data[3] = 0x08;
    data[4] = 0x10;
    data[5] = 0x20;
    data[6] = 0x40;
    data[7] = 0x80;
    data[8] = 0x11;
    data[9] = 0x22;
    
    while(1)
    {        
        hw_lcd_write_n_data( 0x02, data, 10 );
        vTaskDelay( pdMS_TO_TICKS(1000) );   
    }
}


inline void hw_lcd_write_n_data( uint32_t command, uint8_t* data, uint32_t data_len )      
{           
    LCD_CAM.lcd_user.lcd_dout_cyclelen = data_len - 1;  // 0 = 1 single byte. LCD_CAM.lcd_user.lcd_always_out_en = 0;

    LCD_CAM.lcd_user.lcd_cmd = 1;   
    LCD_CAM.lcd_user.lcd_dout = 1;
    
    LCD_CAM.lcd_cmd_val.lcd_cmd_value = command;
     
    hw_lcd_dma_tx_push_n_data( 0, data, data_len );

//    LCD_CAM.lcd_user.lcd_update = 1;  
//    LCD_CAM.lcd_user.lcd_start = 1;   
}


inline void hw_lcd_dma_tx_push_n_data( uint32_t channel, uint8_t* data, uint32_t data_len )
{ 
    printf("\x1b[31m");  // Red text

    printf("dma tx idle: %s\n", hw_lcd_dma_tx_idle(0) ? "IDLE" : "BUSY" );
    
    printf("L1_fifo: %s\n", hw_lcd_dma_L1_fifo_empty(0) ? "EMPTY" : "NOT_EMPTY" );
    printf("L1_fifo: %s\n", hw_lcd_dma_L1_fifo_full(0) ?  "FULL" : "NOT_FULL" );
    printf("L1_count: %u\n\n", hw_lcd_dma_L1_fifo_count(0) );

    printf("L2_fifo: %s\n", hw_lcd_dma_L2_fifo_empty(0) ? "EMPTY" : "NOT_EMPTY" );
    printf("L2_fifo: %s\n", hw_lcd_dma_L2_fifo_full(0) ?  "FULL" : "NOT_FULL" );
    printf("L2_count: %u\n\n", hw_lcd_dma_L2_fifo_count(0) );

    printf("L3_fifo: %s\n", hw_lcd_dma_L3_fifo_empty(0) ? "EMPTY" : "NOT_EMPTY" );
    printf("L3_fifo: %s\n", hw_lcd_dma_L3_fifo_full(0) ?  "FULL" : "NOT_FULL" );
    printf("L3_count: %u\n\n", hw_lcd_dma_L3_fifo_count(0) );

    printf("ovf_l1: %s\n", GDMA.channel[channel].out.int_raw.outfifo_ovf_l1 ? "OVERFLOW" : "NOT_OVERFLOW" );
    printf("ovf_l3: %s\n", GDMA.channel[channel].out.int_raw.outfifo_ovf_l3 ? "OVERFLOW" : "NOT_OVERFLOW" );

    printf("udf_l1: %s\n", GDMA.channel[channel].out.int_raw.outfifo_udf_l1 ? "UNDERLOW" : "NOT_UNDERFLOW" );
    printf("udf_l3: %s\n\n\n", GDMA.channel[channel].out.int_raw.outfifo_udf_l3 ? "UNDERLOW" : "NOT_UNDERFLOW" );

    uint32_t t;
    bool s = 0;

    for( uint32_t i = 0 ; i < data_len ; i++ )
    {       
        // while( hw_lcd_dma_L1_fifo_full(channel) );
        
        t = 0;

        while( hw_lcd_dma_L1_fifo_full(channel) )
        {
            t++;

            if( t == 1000 )
            {
                s = 1;
                goto stop;
            }            
        }

        GDMA.channel[channel].out.push.outfifo_wdata = data[i];  
        GDMA.channel[channel].out.push.outfifo_push = 1;                    
    }

stop:
    printf("\x1b[34m");  // blue text

    printf("dma tx idle: %s\n", hw_lcd_dma_tx_idle(0) ? "IDLE" : "BUSY" );
    
    printf("L1_fifo: %s\n", hw_lcd_dma_L1_fifo_empty(0) ? "EMPTY" : "NOT_EMPTY" );
    printf("L1_fifo: %s\n", hw_lcd_dma_L1_fifo_full(0) ?  "FULL" : "NOT_FULL" );
    printf("L1_count: %u\n\n", hw_lcd_dma_L1_fifo_count(0) );

    printf("L2_fifo: %s\n", hw_lcd_dma_L2_fifo_empty(0) ? "EMPTY" : "NOT_EMPTY" );
    printf("L2_fifo: %s\n", hw_lcd_dma_L2_fifo_full(0) ?  "FULL" : "NOT_FULL" );
    printf("L2_count: %u\n\n", hw_lcd_dma_L2_fifo_count(0) );

    printf("L3_fifo: %s\n", hw_lcd_dma_L3_fifo_empty(0) ? "EMPTY" : "NOT_EMPTY" );
    printf("L3_fifo: %s\n", hw_lcd_dma_L3_fifo_full(0) ?  "FULL" : "NOT_FULL" );
    printf("L3_count: %u\n\n", hw_lcd_dma_L3_fifo_count(0) );

    printf("ovf_l1: %s\n", GDMA.channel[channel].out.int_raw.outfifo_ovf_l1 ? "OVERFLOW" : "NOT_OVERFLOW" );
    printf("ovf_l3: %s\n", GDMA.channel[channel].out.int_raw.outfifo_ovf_l3 ? "OVERFLOW" : "NOT_OVERFLOW" );

    printf("udf_l1: %s\n", GDMA.channel[channel].out.int_raw.outfifo_udf_l1 ? "UNDERLOW" : "NOT_UNDERFLOW" );
    printf("udf_l3: %s\n\n\n", GDMA.channel[channel].out.int_raw.outfifo_udf_l3 ? "UNDERLOW" : "NOT_UNDERFLOW" ); 

    if( s )
        while(1);
}
ESP-IDF MONITOR:

Code: Select all

I (688) HW_LCD_DMA: GDMA HW Version: 0x02101180

I (695) HW_LCD: HW_LCD Information:
I (700) HW_LCD: LCD_CAM HW Version: 33566752
I (705) HW_LCD: HW_LCD_FREQ_HZ = 20 MHz
I (711) HW_LCD: WR io num = 4
I (716) HW_LCD: DC io num = 5
I (720) HW_LCD: CS io num = 6
I (725) HW_LCD: HW_LCD BUS Data Width = 8
I (730) HW_LCD: Data[0] = 7
I (735) HW_LCD: Data[1] = 15
I (739) HW_LCD: Data[2] = 16
I (744) HW_LCD: Data[3] = 17
I (748) HW_LCD: Data[4] = 18
I (753) HW_LCD: Data[5] = 8
I (757) HW_LCD: Data[6] = 3
I (762) HW_LCD: Data[7] = 46
r = ESP_OK

dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: EMPTY
L2_fifo: NOT_FULL
L2_count: 0

L3_fifo: EMPTY
L3_fifo: NOT_FULL
L3_count: 0

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: EMPTY
L2_fifo: NOT_FULL
L2_count: 0

L3_fifo: NOT_EMPTY
L3_fifo: NOT_FULL
L3_count: 8

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: EMPTY
L2_fifo: NOT_FULL
L2_count: 0

L3_fifo: NOT_EMPTY
L3_fifo: NOT_FULL
L3_count: 8

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: EMPTY
L2_fifo: NOT_FULL
L2_count: 0

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: EMPTY
L2_fifo: NOT_FULL
L2_count: 0

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 1

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 1

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 3

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 3

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 4

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 4

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 5

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 5

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 6

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 6

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 8

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 8

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 9

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 9

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: FULL
L2_count: 10

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: FULL
L2_count: 10

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 14

L2_fifo: NOT_EMPTY
L2_fifo: FULL
L2_count: 10

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 14

L2_fifo: NOT_EMPTY
L2_fifo: FULL
L2_count: 10

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: FULL
L1_count: 16

L2_fifo: NOT_EMPTY
L2_fifo: FULL
L2_count: 10

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


E (17174) task_wdt: Task watchdog got triggered. The following tasks did not reset the watchdog in time:
E (17174) task_wdt:  - IDLE (CPU 0)
E (17174) task_wdt: Tasks currently running:
E (17174) task_wdt: CPU 0: main
E (17174) task_wdt: CPU 1: IDLE
E (17174) task_wdt: Print CPU 0 (current core) backtrace


Backtrace:0x42008686:0x3FC95F400x4037A78A:0x3FC95F60 0x42005F7C:0x3FCF48C0 0x42005969:0x3FCF48E0 0x420054F5:0x3FCF4900 0x420179A1:0x3FCF4940 0x4037FEF1:0x3FCF4960 
0x42008686: task_wdt_isr at C:/esp-idf/components/esp_system/task_wdt.c:183 (discriminator 3)

0x4037a78a: _xt_lowint1 at C:/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1111

0x42005f7c: hw_lcd_dma_tx_push_n_data at C:\esp32Projects\WSS_SERVER_AND_UI_INTEGRATION_S3\build/../components/ui/drv/src/hw_lcd_dma.c:720 (discriminator 4)

0x42005969: hw_lcd_write_n_data at C:\esp32Projects\WSS_SERVER_AND_UI_INTEGRATION_S3\build/../components/ui/drv/src/hw_lcd.c:635

0x420054f5: app_main at C:\esp32Projects\WSS_SERVER_AND_UI_INTEGRATION_S3\build/../main/src/main.c:84 (discriminator 1)

0x420179a1: main_task at C:/esp-idf/components/freertos/port/port_common.c:129 (discriminator 2)

0x4037fef1: vPortTaskWrapper at C:/esp-idf/components/freertos/port/xtensa/port.c:130


E (17174) task_wdt: Print CPU 1 backtrace


Backtrace:0x4037BD7D:0x3FC965400x4037A78A:0x3FC96560 0x400559DD:0x3FCF5900  |<-CORRUPTED
0x4037bd7d: esp_crosscore_isr at C:/esp-idf/components/esp_system/crosscore_int.c:92

0x4037a78a: _xt_lowint1 at C:/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1111
@ESP_Sprite,

Did you show this to the digital team ?

Thank's.

Baldhead
Posts: 341
Joined: Sun Mar 31, 2019 5:16 am

Re: ESP32-S3 LCD and I2S FULL documentation

Postby Baldhead » Wed Dec 29, 2021 12:33 am

@ESP_Sprite,

If i set "GDMA.sram_size[channel].out.out_size = 14", following this logic:

// gdma_struct.h
GDMA.sram_size[channel].out.out_size = 14; // This register is used to configure the size of L2 Tx FIFO for Tx channel 0.
// 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes.

All multiples of 8: ( relevant or not?! )
0: 16 bytes = 2*8
1: 24 bytes = 3*8
2: 32 bytes = 4*8
3: 40 bytes = 5*8
4: 48 bytes = 6*8
5: 56 bytes = 7*8
6: 64 bytes = 8*8
7: 72 bytes = 9*8
8: 80 bytes = 10*8
9: 88 bytes = 11*8
10: 96 bytes = 12*8
11: 104 bytes = 13*8
12: 112 bytes = 14*8
13: 120 bytes = 15*8
14: 128 bytes = 16*8

This happens:

dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: FULL
L1_count: 16

L2_fifo: NOT_EMPTY
L2_fifo: FULL
L2_count: 16

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW

Esp32-s3 technical reference manual: Pre-release v0.3, page 78
L1FIFO, L2FIFO and L3FIFO have fixed depth: 24, 128, and 16 bytes, respectively.

Measured:
L1 size = 16 bytes. L1 count unit is 1 byte.
L2 size = 128 bytes. L2 count unit is 8 bytes.
L3 size = 16 bytes. L3 count unit is 1 byte.

Code: Select all

I (687) HW_LCD_DMA: GDMA HW Version: 0x02101180

I (694) HW_LCD: HW_LCD Information:
I (699) HW_LCD: LCD_CAM HW Version: 33566752
I (704) HW_LCD: HW_LCD_FREQ_HZ = 20 MHz
I (710) HW_LCD: WR io num = 4
I (715) HW_LCD: DC io num = 5
I (719) HW_LCD: CS io num = 6
I (724) HW_LCD: HW_LCD BUS Data Width = 8
I (729) HW_LCD: Data[0] = 7
I (734) HW_LCD: Data[1] = 15
I (738) HW_LCD: Data[2] = 16
I (743) HW_LCD: Data[3] = 17
I (747) HW_LCD: Data[4] = 18
I (752) HW_LCD: Data[5] = 8
I (756) HW_LCD: Data[6] = 3
I (761) HW_LCD: Data[7] = 46
r = ESP_OK

dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: EMPTY
L2_fifo: NOT_FULL
L2_count: 0

L3_fifo: EMPTY
L3_fifo: NOT_FULL
L3_count: 0

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: EMPTY
L2_fifo: NOT_FULL
L2_count: 0

L3_fifo: NOT_EMPTY
L3_fifo: NOT_FULL
L3_count: 8

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: EMPTY
L2_fifo: NOT_FULL
L2_count: 0

L3_fifo: NOT_EMPTY
L3_fifo: NOT_FULL
L3_count: 8

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: EMPTY
L2_fifo: NOT_FULL
L2_count: 0

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: EMPTY
L2_fifo: NOT_FULL
L2_count: 0

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 1

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 1

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 3

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 3

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 4

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 4

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 5

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 5

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 6

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 6

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 8

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 8

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 9

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 9

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 10

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 10

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 11

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 11

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 13

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 13

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 14

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 14

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 15

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 15

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: FULL
L2_count: 16

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: FULL
L2_count: 16

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: FULL
L1_count: 16

L2_fifo: NOT_EMPTY
L2_fifo: FULL
L2_count: 16

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: FULL
L1_count: 16

L2_fifo: NOT_EMPTY
L2_fifo: FULL
L2_count: 16

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: FULL
L1_count: 16

L2_fifo: NOT_EMPTY
L2_fifo: FULL
L2_count: 16

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


E (22355) task_wdt: Task watchdog got triggered. The following tasks did not reset the watchdog in time:
E (22355) task_wdt:  - IDLE (CPU 0)
E (22355) task_wdt: Tasks currently running:
E (22355) task_wdt: CPU 0: main
E (22355) task_wdt: CPU 1: IDLE
E (22355) task_wdt: Print CPU 0 (current core) backtrace


Backtrace:0x42008686:0x3FC95F400x4037A78A:0x3FC95F60 0x42005F7C:0x3FCF48C0 0x42005969:0x3FCF48E0 0x420054F5:0x3FCF4900 0x420179A1:0x3FCF4940 0x4037FEF1:0x3FCF4960 
0x42008686: task_wdt_isr at C:/esp-idf/components/esp_system/task_wdt.c:183 (discriminator 3)

0x4037a78a: _xt_lowint1 at C:/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1111

0x42005f7c: hw_lcd_dma_tx_push_n_data at C:\esp32Projects\WSS_SERVER_AND_UI_INTEGRATION_S3\build/../components/ui/drv/src/hw_lcd_dma.c:724 (discriminator 4)

0x42005969: hw_lcd_write_n_data at C:\esp32Projects\WSS_SERVER_AND_UI_INTEGRATION_S3\build/../components/ui/drv/src/hw_lcd.c:635

0x420054f5: app_main at C:\esp32Projects\WSS_SERVER_AND_UI_INTEGRATION_S3\build/../main/src/main.c:84 (discriminator 1)

0x420179a1: main_task at C:/esp-idf/components/freertos/port/port_common.c:129 (discriminator 2)

0x4037fef1: vPortTaskWrapper at C:/esp-idf/components/freertos/port/xtensa/port.c:130


E (22355) task_wdt: Print CPU 1 backtrace


Backtrace:0x4037BD7D:0x3FC965400x4037A78A:0x3FC96560 0x400559DD:0x3FCF5900  |<-CORRUPTED
0x4037bd7d: esp_crosscore_isr at C:/esp-idf/components/esp_system/crosscore_int.c:92

0x4037a78a: _xt_lowint1 at C:/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1111
Last edited by Baldhead on Wed Dec 29, 2021 2:18 am, edited 1 time in total.

Baldhead
Posts: 341
Joined: Sun Mar 31, 2019 5:16 am

Re: ESP32-S3 LCD and I2S FULL documentation

Postby Baldhead » Wed Dec 29, 2021 1:46 am

@ESP_Sprite,

GDMA.sram_size[channel].out.out_size = 127; // Register size is 7 bits.

Code: Select all

I (687) HW_LCD_DMA: GDMA HW Version: 0x02101180

I (694) HW_LCD: HW_LCD Information:
I (699) HW_LCD: LCD_CAM HW Version: 33566752
I (704) HW_LCD: HW_LCD_FREQ_HZ = 20 MHz
I (710) HW_LCD: WR io num = 4
I (715) HW_LCD: DC io num = 5
I (719) HW_LCD: CS io num = 6
I (724) HW_LCD: HW_LCD BUS Data Width = 8
I (729) HW_LCD: Data[0] = 7
I (734) HW_LCD: Data[1] = 15
I (738) HW_LCD: Data[2] = 16
I (743) HW_LCD: Data[3] = 17
I (747) HW_LCD: Data[4] = 18
I (752) HW_LCD: Data[5] = 8
I (756) HW_LCD: Data[6] = 3
I (761) HW_LCD: Data[7] = 46
r = ESP_OK

dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: EMPTY
L2_fifo: NOT_FULL
L2_count: 0

L3_fifo: EMPTY
L3_fifo: NOT_FULL
L3_count: 0

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: EMPTY
L2_fifo: NOT_FULL
L2_count: 0

L3_fifo: NOT_EMPTY
L3_fifo: NOT_FULL
L3_count: 8

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: EMPTY
L2_fifo: NOT_FULL
L2_count: 0

L3_fifo: NOT_EMPTY
L3_fifo: NOT_FULL
L3_count: 8

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: EMPTY
L2_fifo: NOT_FULL
L2_count: 0

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: EMPTY
L2_fifo: NOT_FULL
L2_count: 0

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 1

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 1

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 3

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 3

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 4

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 4

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 5

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 5

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 6

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 6

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 8

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 8

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 9

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 9

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 10

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 10

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 11

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 11

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 13

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 13

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 14

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 14

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 15

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 15

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 16

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 16

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 18

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 18

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 19

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 19

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 20

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 20

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 21

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 21

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 23

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 23

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 24

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 24

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 25

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 25

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 26

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 26

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 28

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 28

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 29

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 29

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 30

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 30

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 31

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 31

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 33

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 33

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 34

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 34

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 35

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 35

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 36

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 36

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 38

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 38

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 39

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 39

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 40

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 40

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 41

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 41

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 43

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 43

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 44

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 44

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 45

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 45

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 46

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 46

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 48

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 48

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 49

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 49

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 50

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 50

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 51

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 51

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 53

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 53

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 54

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 54

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 55

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 55

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 56

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 56

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 58

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 58

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 59

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 59

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 60

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 60

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 61

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 61

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 63

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 63

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 64

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 64

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 65

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 65

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 66

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 66

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 68

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 68

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 69

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 69

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 70

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 70

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 71

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 71

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 73

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 73

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 74

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 74

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 75

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 75

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 76

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 76

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 78

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 78

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 79

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 79

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 80

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 80

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 81

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 81

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 83

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 83

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 84

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 84

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 85

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 85

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 86

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 86

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 88

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 88

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 89

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 89

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 90

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 90

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 91

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 91

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 93

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 93

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 94

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 94

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 95

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 95

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 96

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 96

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 98

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 98

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 99

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 99

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 100

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 100

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 101

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 101

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 103

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 103

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 104

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 104

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 105

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 105

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 106

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 106

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 108

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 108

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 109

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 109

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 110

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 110

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 111

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 111

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 113

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 113

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 114

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 114

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 115

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 115

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 116

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 116

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 118

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 118

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 119

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 119

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 120

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 120

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 121

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 121

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 123

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 123

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 124

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 124

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 125

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 4

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 125

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 126

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 6

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 126

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 0

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: EMPTY
L1_fifo: NOT_FULL
L1_count: 0

L2_fifo: NOT_EMPTY
L2_fifo: NOT_FULL
L2_count: 0

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: FULL
L2_count: 1

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 2

L2_fifo: NOT_EMPTY
L2_fifo: FULL
L2_count: 1

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 12

L2_fifo: NOT_EMPTY
L2_fifo: FULL
L2_count: 1

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: NOT_FULL
L1_count: 12

L2_fifo: NOT_EMPTY
L2_fifo: FULL
L2_count: 1

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


dma tx idle: IDLE
L1_fifo: NOT_EMPTY
L1_fifo: FULL
L1_count: 16

L2_fifo: NOT_EMPTY
L2_fifo: FULL
L2_count: 1

L3_fifo: NOT_EMPTY
L3_fifo: FULL
L3_count: 16

ovf_l1: NOT_OVERFLOW
ovf_l3: NOT_OVERFLOW
udf_l1: NOT_UNDERFLOW
udf_l3: NOT_UNDERFLOW


E (115640) task_wdt: Task watchdog got triggered. The following tasks did not reset the watchdog in time:
E (115640) task_wdt:  - IDLE (CPU 0)
E (115640) task_wdt: Tasks currently running:
E (115640) task_wdt: CPU 0: main
E (115640) task_wdt: CPU 1: IDLE
E (115640) task_wdt: Print CPU 0 (current core) backtrace


Backtrace:0x42008682:0x3FC95F400x4037A78A:0x3FC95F60 0x42005F78:0x3FCF48C0 0x42005969:0x3FCF48E0 0x420054F5:0x3FCF4900 0x4201799D:0x3FCF4940 0x4037FEF1:0x3FCF4960 
0x42008682: task_wdt_isr at C:/esp-idf/components/esp_system/task_wdt.c:183 (discriminator 3)

0x4037a78a: _xt_lowint1 at C:/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1111

0x42005f78: hw_lcd_dma_tx_push_n_data at C:\esp32Projects\WSS_SERVER_AND_UI_INTEGRATION_S3\build/../components/ui/drv/src/hw_lcd_dma.c:724 (discriminator 4)

0x42005969: hw_lcd_write_n_data at C:\esp32Projects\WSS_SERVER_AND_UI_INTEGRATION_S3\build/../components/ui/drv/src/hw_lcd.c:635

0x420054f5: app_main at C:\esp32Projects\WSS_SERVER_AND_UI_INTEGRATION_S3\build/../main/src/main.c:84 (discriminator 1)

0x4201799d: main_task at C:/esp-idf/components/freertos/port/port_common.c:129 (discriminator 2)

0x4037fef1: vPortTaskWrapper at C:/esp-idf/components/freertos/port/xtensa/port.c:130


E (115640) task_wdt: Print CPU 1 backtrace


Backtrace:0x4037BD7D:0x3FC965400x4037A78A:0x3FC96560 0x400559DD:0x3FCF5900  |<-CORRUPTED
0x4037bd7d: esp_crosscore_isr at C:/esp-idf/components/esp_system/crosscore_int.c:92

0x4037a78a: _xt_lowint1 at C:/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1111

Baldhead
Posts: 341
Joined: Sun Mar 31, 2019 5:16 am

Re: ESP32-S3 LCD and I2S FULL documentation

Postby Baldhead » Fri Dec 31, 2021 5:02 am

@ESP_Sprite,

I tested the program with the code below and it almost worked.

The problem is that second clock in the picture in annex shouldn't exist.

Should be:
command
0x02

Data
0x01, 0x02, 0x04, 0x08 // hw_lcd_write_n_data( 0x02, data, 4 );

Any suggestions from the digital team maybe ?!

Code: Select all

void app_main(void)
{  
    esp_err_t r = hw_lcd_init();
    printf("r = %s\n\n", esp_err_to_name(r));
    
    uint8_t data[8];

    data[0] = 0x01;
    data[1] = 0x02;
    data[2] = 0x04;
    data[3] = 0x08;
    data[4] = 0x00;
    data[5] = 0x00;
    data[6] = 0x00;
    data[7] = 0x00;
    
    while(1)
    {        
        hw_lcd_write_n_data( 0x02, data, 5 );  // 4
        vTaskDelay( pdMS_TO_TICKS(1000) );   
    }
}

inline void hw_lcd_write_n_data( uint32_t command, uint8_t* data, uint32_t data_len )      
{   
    LCD_CAM.lcd_user.lcd_always_out_en = 0;  // 0 = fifo mode. 1 = dma mode 
    
    hw_lcd_afifo_reset();
    hw_lcd_dma_tx_fifo_reset( 0 );
    
    LCD_CAM.lcd_user.lcd_dout_cyclelen = data_len - 1;  // 0 = 1 single byte. LCD_CAM.lcd_user.lcd_always_out_en = 0;
        
    LCD_CAM.lcd_user.lcd_cmd = 1;   // R/W; bitpos: [26]; default: 0. 1: Be able to send command in LCD sequence when LCD starts. 0: Disable.  
    LCD_CAM.lcd_user.lcd_dout = 1;  // R/W; bitpos: [24]; default: 0. 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.
    
    LCD_CAM.lcd_cmd_val.lcd_cmd_value = command;  // R/W; bitpos: [31:0]; default: 0. The LCD write command value. 
     
    hw_lcd_dma_tx_push_n_data( 0, data, 8 );  // hw_lcd_dma_tx_push_n_data( 0, data, data_len );

    LCD_CAM.lcd_user.lcd_update = 1;  // R/W; bitpos: [20]; default: 0. 1: Update LCD registers, will be cleared by hardware. 0 : Not care. Update parameters before start transaction.
    LCD_CAM.lcd_user.lcd_start = 1;   // R/W; bitpos: [27]; default: 0. LCD start sending data enable signal, valid in high level.
}


inline void hw_lcd_dma_tx_push_n_data( uint32_t channel, uint8_t* data, uint32_t data_len )
{     
    printf("\x1b[31m");  // Red text

    printf("dma tx idle: %s\n", hw_lcd_dma_tx_idle(0) ? "IDLE" : "BUSY" );
    
    printf("L1_fifo: %s\n", hw_lcd_dma_L1_fifo_empty(0) ? "EMPTY" : "NOT_EMPTY" );
    printf("L1_fifo: %s\n", hw_lcd_dma_L1_fifo_full(0) ?  "FULL" : "NOT_FULL" );
    printf("L1_count: %u\n\n", hw_lcd_dma_L1_fifo_count(0) );

    printf("L2_fifo: %s\n", hw_lcd_dma_L2_fifo_empty(0) ? "EMPTY" : "NOT_EMPTY" );
    printf("L2_fifo: %s\n", hw_lcd_dma_L2_fifo_full(0) ?  "FULL" : "NOT_FULL" );
    printf("L2_count: %u\n\n", hw_lcd_dma_L2_fifo_count(0) );

    printf("L3_fifo: %s\n", hw_lcd_dma_L3_fifo_empty(0) ? "EMPTY" : "NOT_EMPTY" );
    printf("L3_fifo: %s\n", hw_lcd_dma_L3_fifo_full(0) ?  "FULL" : "NOT_FULL" );
    printf("L3_count: %u\n\n", hw_lcd_dma_L3_fifo_count(0) );

    printf("ovf_l1: %s\n", GDMA.channel[channel].out.int_raw.outfifo_ovf_l1 ? "OVERFLOW" : "NOT_OVERFLOW" );
    printf("ovf_l3: %s\n", GDMA.channel[channel].out.int_raw.outfifo_ovf_l3 ? "OVERFLOW" : "NOT_OVERFLOW" );

    printf("udf_l1: %s\n", GDMA.channel[channel].out.int_raw.outfifo_udf_l1 ? "UNDERLOW" : "NOT_UNDERFLOW" );
    printf("udf_l3: %s\n\n\n", GDMA.channel[channel].out.int_raw.outfifo_udf_l3 ? "UNDERLOW" : "NOT_UNDERFLOW" );

    uint32_t t;
    bool s = 0;

    for( uint32_t i = 0 ; i < data_len ; i++ )
    {       
        // while( hw_lcd_dma_L1_fifo_full(channel) );
        
        t = 0;

        while( hw_lcd_dma_L1_fifo_full(channel) )
        {
            t++;

            if( t == 1000 )
            {
                s = 1;
                goto stop;
            }            
        }

        GDMA.channel[channel].out.push.outfifo_wdata = data[i];  // This register stores the data that need to be pushed into DMA FIFO.
        GDMA.channel[channel].out.push.outfifo_push = 1;         // Set this bit to push data into DMA FIFO.           
    }

stop:

    printf("\x1b[34m");  // blue text

    printf("dma tx idle: %s\n", hw_lcd_dma_tx_idle(0) ? "IDLE" : "BUSY" );
    
    printf("L1_fifo: %s\n", hw_lcd_dma_L1_fifo_empty(0) ? "EMPTY" : "NOT_EMPTY" );
    printf("L1_fifo: %s\n", hw_lcd_dma_L1_fifo_full(0) ?  "FULL" : "NOT_FULL" );
    printf("L1_count: %u\n\n", hw_lcd_dma_L1_fifo_count(0) );

    printf("L2_fifo: %s\n", hw_lcd_dma_L2_fifo_empty(0) ? "EMPTY" : "NOT_EMPTY" );
    printf("L2_fifo: %s\n", hw_lcd_dma_L2_fifo_full(0) ?  "FULL" : "NOT_FULL" );
    printf("L2_count: %u\n\n", hw_lcd_dma_L2_fifo_count(0) );

    printf("L3_fifo: %s\n", hw_lcd_dma_L3_fifo_empty(0) ? "EMPTY" : "NOT_EMPTY" );
    printf("L3_fifo: %s\n", hw_lcd_dma_L3_fifo_full(0) ?  "FULL" : "NOT_FULL" );
    printf("L3_count: %u\n\n", hw_lcd_dma_L3_fifo_count(0) );

    printf("ovf_l1: %s\n", GDMA.channel[channel].out.int_raw.outfifo_ovf_l1 ? "OVERFLOW" : "NOT_OVERFLOW" );
    printf("ovf_l3: %s\n", GDMA.channel[channel].out.int_raw.outfifo_ovf_l3 ? "OVERFLOW" : "NOT_OVERFLOW" );

    printf("udf_l1: %s\n", GDMA.channel[channel].out.int_raw.outfifo_udf_l1 ? "UNDERLOW" : "NOT_UNDERFLOW" );
    printf("udf_l3: %s\n\n\n", GDMA.channel[channel].out.int_raw.outfifo_udf_l3 ? "UNDERLOW" : "NOT_UNDERFLOW" ); 


    if( s )
        while(1);
}


inline void hw_lcd_afifo_reset()
{
    LCD_CAM.lcd_misc.lcd_afifo_reset = 1;
    LCD_CAM.lcd_misc.lcd_afifo_reset = 0;
}


inline void hw_lcd_dma_tx_fifo_reset( uint32_t channel )
{
    GDMA.channel[channel].out.conf0.out_rst = 1;  // This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.
    GDMA.channel[channel].out.conf0.out_rst = 0;
}    
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Baldhead
Posts: 341
Joined: Sun Mar 31, 2019 5:16 am

Re: ESP32-S3 LCD and I2S FULL documentation

Postby Baldhead » Wed Jan 05, 2022 5:37 am

@ESP_Sprite,

Some suggestion on last post ?

Baldhead
Posts: 341
Joined: Sun Mar 31, 2019 5:16 am

Re: ESP32-S3 LCD and I2S FULL documentation

Postby Baldhead » Fri Jan 21, 2022 2:05 pm

@ESP_Sprite,

I'm on vacation this month and "luckily" i still got covid.

Nothing about this topic yet ???

Thank's.

Baldhead
Posts: 341
Joined: Sun Mar 31, 2019 5:16 am

Re: ESP32-S3 LCD and I2S FULL documentation

Postby Baldhead » Tue Jan 25, 2022 10:10 pm

???????

Baldhead
Posts: 341
Joined: Sun Mar 31, 2019 5:16 am

Re: ESP32-S3 LCD and I2S FULL documentation

Postby Baldhead » Wed Jan 26, 2022 2:57 pm

More than 11 thousand views on this topic here on the forum.

A month to give an answer and so far nothing.
Espressif treats customers like clowns.

It wasn't me who designed the esp32-s3 chip.

Espressif team can help me or not ????

ESP_Sprite
Posts: 6386
Joined: Thu Nov 26, 2015 4:08 am

Re: ESP32-S3 LCD and I2S FULL documentation

Postby ESP_Sprite » Thu Jan 27, 2022 7:22 am

As I said before, official answer is 'wait until we finish the TRM, or contact the sales team if you're going to run production-volume numbers with this'.

With that being said, I do need to apologize as I offered to get you information informally, and I left you hanging there and I can imagine you feel frustrated with that. Sorry, that should not have happened.

With that being said, the issue is that I can't really find much wrong with your code... I have a few things you could check, maybe:
- Do you have LCD_CAM_LCD_DUMMY and LCD_CAM_LCD_CMD_2_CYCLE_EN set to 0?
- Not sure if that's 100% sure an issue if it isn't, but is data[] 4-byte aligned?
- Is there any way you can check your code with actual DMA, instead of pushing into the FIFO? As I said before, we think pushing into the FIFO should work, but it's relatively untested.

Baldhead
Posts: 341
Joined: Sun Mar 31, 2019 5:16 am

Re: ESP32-S3 LCD and I2S FULL documentation

Postby Baldhead » Mon Feb 07, 2022 11:53 pm

ESP_Sprite wrote:
Thu Jan 27, 2022 7:22 am
With that being said, the issue is that I can't really find much wrong with your code... I have a few things you could check, maybe:
- Do you have LCD_CAM_LCD_DUMMY and LCD_CAM_LCD_CMD_2_CYCLE_EN set to 0?
Yes. The default value.

- Not sure if that's 100% sure an issue if it isn't, but is data[] 4-byte aligned ?
I declared data[] statically.
How can i align this data[] ?

- Is there any way you can check your code with actual DMA, instead of pushing into the FIFO? As I said before, we think pushing into the FIFO should work, but it's relatively untested.
I will try as soon as possible.
But the digital team can't give some tips about pushing data into fifo ?
Maybe a hardware test inside espressif.

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